ADE7754 Datasheet, PDF (39/44 Pages) Analog Devices – ADE7754

PRELIMINARY TECHNICAL DATA
ADE7754
Gain Register (18h)
The Gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing
to the GAIN register. Table X below summarizes the functionality of each bit in the GAIN register .
Table X GAIN Register
Bit
Bit
Default
Location Mnemonic Value Description
0-1
PGA1
0
2
ABS
0
3
NOLOAD 0
4
RESERVED -
5-6
PGA2
0
7
RESERVED -
These bits are used to select the Gain of the current channels inputs.
bit 1
bit 0
0
0
PGA1=1
0
1
PGA1=2
1
0
PGA1=4
0
0
Reserved
The sum of the absolute active energies is done in the ANERGY and LAENERGY
registers when this bit is set to logic one. The regular sum is done when this bit is set to
logic zero - default mode.
The active energy of each phase is not accumulated in the total active energy registers if
the instantaneous active power is lower than the no-load threshold when this bit is set to
logic zero, this mode is selected by default.
This is intended for factory testing only and should be left at zero.
These bits are used to select the Gain of the voltage channels inputs.
bit 6
bit 5
0
0
PGA2=1
0
1
PGA2=2
1
0
PGA2=4
0
0
Reserved
This is intended for factory testing only and should be left at zero.
CFNUM Register (25h)
The CF scaling numerator and the sign of the active energy per phase are defined by writing/reading to the CFNUM register.
Table XI below summarizes the functionality of each bit in the CFNUM register .
Table XI CFNUM Register
Bit
Bit
Default
Location Mnemonic Value Description
0-Bh
CFN
0
Ch
NEGA
0
Dh
NEGB
0
Eh
NEGC
0
Fh
RESERVED
CF Scaling Numerator register. The content of this register is used in the numerator of
CF output scaling.
The sign of the phase A instantaneous active power is available in this bit. Logic zero and
Logic one correspond to Positive and negative active power respectively. The functionality
of this bit is enabled by setting bit 5 of the WATMode register to logic one. When disabled
NEGA is equal to its default value.
The sign of the phase B instantaneous active power is available in this bit. Logic zero and
Logic one correspond to Positive and negative active power respectively. The functionality
of this bit is enabled by setting bit 4 of the WATMode register to logic one. When disabled
NEGB is equal to its default value.
The sign of the phase C instantaneous active power is available in this bit. Logic zero and
Logic one correspond to Positive and negative active power respectively. The functionality
of this bit is enabled by setting bit 3 of the WATMode register to logic one. When disabled
NEGC is equal to its default value.
REV. PrG 01/03
–39–