ADE7754 Datasheet, PDF (33/44 Pages) Analog Devices – ADE7754

PRELIMINARY TECHNICAL DATA
ADE7754
ADE7754 INTERRUPTS
ADE7754 Interrupts are managed through the Interrupt
Status register (STATUS[15:0], Address 10h) and the Inter-
rupt Mask register (MASK[15:0], Address 0Fh). When an
interrupt event occurs in the ADE7754, the corresponding
flag in the Interrupt Status register is set to a logic one - see
ADE7754 Interrupt Status register. If the mask bit for this interrupt
in the Interrupt Mask register is logic one, then the IRQ logic
output goes active low. The flag bits in the Interrupt Status
register are set irrespective of the state of the mask bits.
In order to determine the source of the interrupt, the system
master (MCU) should perform a read from the Reset Inter-
rupt Status register with reset. This is achieved by carrying
out a read from address 11h. The IRQ output will go logic
high on completion of the Interrupt Status register read
command—see Interrupt timing. When carrying out a read with
reset the ADE7754 is designed to ensure that no interrupt
events are missed. If an interrupt event occurs just as the
Interrupt Status register is being read, the event will not be
lost and the IRQ logic output is guaranteed to go high for the
duration of the Interrupt Status register data transfer before
going logic low again to indicate the pending interrupt.
Using the ADE7754 Interrupts with an MCU
Shown in Figure 45 is a timing diagram which illustrates a
suggested implementation of ADE7754 interrupt manage-
ment using an MCU. At time t₁ the IRQ line will go active
low indicating that one or more interrupt events have oc-
curred in the ADE7754. The IRQ logic output should be tied
to a negative edge triggered external interrupt on the MCU.
On detection of the negative edge, the MCU should be
configured to start executing its Interrupt Service Routine
(ISR). On entering the ISR, all interrupts should be disabled
t₁
t₂
IRQ
using the global interrupt mask bit. At this point the MCU
external interrupt flag can be cleared in order to capture
interrupt events which occur during the current ISR. When
the MCU interrupt flag is cleared, a read from the Reset
Interrupt Status register with reset is carried out. This will
cause the IRQ line to be reset logic high (t₂)—see Interrupt
timing. The Reset Interrupt Status register contents are used
to determine the source of the interrupt(s) and hence the
appropriate action to be taken. If a subsequent interrupt event
occurs during the ISR (t₃), that event will be recorded by the
MCU external interrupt flag being set again. On returning
from the ISR, the global interrupt mask bit will be cleared
(same instruction cycle) and the external interrupt flag will
cause the MCU to jump to its ISR once again. This will
ensure that the MCU does not miss any external interrupts.
Interrupt timing
The ADE7754 Serial Interface section should be reviewed first
before reviewing the interrupt timing. As previously de-
scribed, when the IRQ output goes low the MCU ISR must
read the Interrupt Status register in order to determine the
source of the interrupt. When reading the Interrupt Status
register contents, the IRQ output is set high on the last falling
edge of SCLK of the first byte transfer (read Interrupt Status
register command). The IRQ output is held high until the last
bit of the next 8-bit transfer is shifted out (Interrupt Status
register contents). See Figure 46. If an interrupt is pending
at this time, the IRQ output will go low again. If no interrupt
is pending the IRQ output will remain high.
MCU
int. flag set
t₃
Program
Sequence
Jump to Global int. Clear MCU
ISR
Mask
int. flag
Read
Status with
Reset (11h)
ISR Action
( Based on Status contents)
ISR Return
Global int. Mask
Reset
Jump to
ISR
Figure 45– ADE7754 interrupt management
CS
SCLK
DIN
DOUT
IRQ
REV. PrG 01/03
t₁
t₉
0 0 01 0001
Read Status Register Command
t₁₁
DB15
t₁₂
DB8 DB7
DB0
Status Register Contents
Figure 46– ADE7754 interrupt timing
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