AD9864 Datasheet, PDF (39/44 Pages) Analog Devices – IF Digitizing Subsystem

AD9864
Figure 71 shows a typical dual conversion superheterodyne
receiver using the AD9864. An RF tuner is used to select and
downconvert the target signal to a suitable first IF for the
AD9864. A preselect filter may precede the tuner to limit the
RF input to the band of interest. The output of the tuner drives
an IF filter that provides partial suppression of adjacent chan-
nels and interferers that could otherwise limit the receiver’s
dynamic range. The conversion gain of the tuner should be set
such that the peak IF input signal level into the AD9864 is no
greater than –18 dBm to prevent clipping. The AD9864 down-
converts the first IF signal to a second IF that is exactly 1/8 of
the Σ-∆ ADC’s clock rate, i.e., fCLK/8, to simplify the digital
quadrature demodulation process.
This second IF signal is then digitized by the Σ-∆ ADC,
demodulated into its quadrature I and Q components, filtered
via matching decimation filters, and reformatted to enable a
synchronous serial interface to a DSP. In this example, the
AD9864’s LO and CLK synthesizers are both enabled, requiring
some additional passive components (for the synthesizer’s loop
filters and CLK oscillator) and a VCO for the LO synthesizer.
Note that not all of the required decoupling capacitors are
shown. Refer to the previous section and Figure 70 for more
information on required external passive components.
The selection of the first IF frequency is often based on the
availability of low cost standard crystal or SAW filters as well as
system frequency planning considerations. In general, crystal
filters are often used for narrow-band radios having channel
bandwidths below 50 kHz with IFs below 120 MHz, while SAW
filters are more suited for channel bandwidths greater than
50 kHz with IFs greater than 70 MHz. The ultimate stop-band
rejection required by the IF filter will depend on how much
suppression is required at the AD9864’s image band resulting
from downconversion to the second IF. This image band is
offset from the first IF by twice the second IF frequency
(i.e., ± fCLK/4, depending on high- or low-side injection).
The selectivity and bandwidth of the IF filter will depend on
both the magnitude and frequency offset(s) of the adjacent
channel blocker(s) that could overdrive the AD9864’s input or
generate in-band intermodulation components. Further sup-
pression is performed within the AD9864 by its inherent band-
pass response and digital decimation filters. Note that some
applications will require additional application-specific filtering
performed in the DSP that follows the AD9864 to remove the
adjacent channel and/or implement a matched filter for opti-
mum signal detection.
The output data rate of the AD9864, fOUT, should be chosen to
be at least twice the bandwidth or symbol rate of the desired
signal to ensure that the decimation filters provide a flat pass-
band response as well as to allow for postprocessing by a DSP.
Once fOUT is determined, the decimation factor of the digital
filters should be set such that the input clock rate, fCLK, falls
between the AD9864’s rated operating range of 13 MHz to
26 MHz and no significant spurious products related to fCLK fall
within the desired pass band, resulting in a reduction in sensi-
tivity performance. If a spurious component is found to limit
the sensitivity performance, the decimation factor can often be
modified slightly to find a spurious free pass band. Selecting a
higher fCLK is typically more desirable given a choice, since the
first IF’s filtering requirements often depend on the transition
region between the IF frequency and the image band (i.e.,
± fCLK/4). Lastly, the output SSI clock rate, fCLKOUT, and digital
driver strength should be set to their lowest possible settings to
minimize the potential harmful effects of digital induced noise
while preserving a reliable data link to the DSP. Note that the
SSICRA, SSICRB, and SSIORD registers, i.e., 0x18, 0x19, and
0x1A, provide a large degree of flexibility for optimization of
the SSI interface.
Syncronization of Multiple AD9864S
Some applications, such as receiver diversity and beam steering,
may require two or more AD9864s operating in parallel while
maintaining synchronization. Figure 71 shows an example of
how multiple AD9864s can be cascaded, with one device serv-
ing as the master and the other devices serving as the slaves. In
this example, all of the devices have the same SPI register con-
figuration since they share the same SPI interface to the DSP.
Since the state of each of the AD9864’s internal counters is
unknown upon initialization, synchronization of the devices is
required via a SYNCB pulse (see Figure 36) to synchronize their
digital filters and ensure precise time alignment of the data
streams.
Although all of the devices’ synthesizers are enabled, the LO
and CLK signals for the slave(s) are derived from the masters’
synthesizers and are referenced to an external crystal oscillator.
All of the necessary external components(i.e., loop filters,
varactor, LC, and VCO) required to ensure proper closed-loop
operation of these synthesizers are included.
Note that although the VCO output of the LO synthesizer is
ac-coupled to the slave’s LO input(s), all of the CLK inputs of
the devices must be dc-coupled if the AD9864’s CLK oscillators
are enabled. This is because of the dc current required by the
CLK oscillators in each device. In essence, these negative
impedance cores are operating in parallel, increasing the
effective Q of the LC resonator circuit. RBIAS should be sized
such that the sum of the oscillators’ dc bias currents maintains
a common-mode voltage of around 1.6 V.
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