AD9864 Datasheet, PDF (1/44 Pages) Analog Devices – IF Digitizing Subsystem

IF Digitizing Subsystem
AD9864*
FEATURES
10 MHz to 300 MHz input frequency
6.8 kHz to 270 kHz output signal bandwidth
7.5 dB SSB NF
–7.0 dBm IIP3
AGC free range up to –34 dBm
12 dB continuous AGC range
16 dB front end attenuator
Baseband I/Q 16-bit (or 24-bit) serial digital output
LO and sampling clock synthesizers
Programmable decimation factor, output format,
AGC, and sythesizer settings
370 Ω input impedance
2.7 V to 3.6 V supply voltage
Low current consumption: 17 mA
48-lead LFCSP package
PRODUCT OVERVIEW
The AD9864 is a general-purpose IF subsystem that digitizes a
low level 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the
AD9864 consists of a low noise amplifier (LNA), a mixer, a
band-pass Σ-∆ analog-to-digital converter (ADC), and a deci-
mation filter with programmable decimation factor. An auto-
matic gain control (AGC) circuit gives the AD9864 12 dB of
continuous gain adjustment. Auxiliary blocks include both
clock and LO synthesizers.
The high dynamic range of the AD9864 and inherent antialias-
ing provided by the band-pass Σ-∆ converter allow the device to
cope with blocking signals up to 95 dB stronger than the desired
signal. This attribute often reduces the cost of a radio by reduc-
ing IF filtering requirements. Also, it enables multimode radios
of varying channel bandwidths, allowing the IF filter to be
specified for the largest channel bandwidth.
APPLICATIONS
Multimode narrow-band radio products
Analog/digital UHF/VHF FDMA receivers
TETRA, APCO25, GSM/EDGE
Portable and mobile radio products
SATCOM terminals
The SPI® port programs numerous parameters of the AD9864,
allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios,
AGC attenuation and attack/decay time, received signal
strength level, decimation factor, output data format, 16 dB
attenuator, and the selected bias currents.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
The AD9864 is available in a 48-lead LFCSP package and
operates from a single 2.7 V to 3.6 V supply. The total power
consumption is typically 56 mW and a power-down mode is
provided via serial interfacing.
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON IF2P IF2N GCP GCN
–16dB
DAC AGC
AD9864
IFIN
LNA
FREF
∑-∆ ADC
DECIMATION
FILTER
FORMATTING/SSI
CONTROL LOGIC
DOUTA
DOUTB
FS
CLKOUT
LO
SYN
CLK SYN
VOLTAGE
REFERENCE
SPI
IOUTL
LOP LON
LO VCO AND
LOOP FILTER
IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB
LOOP FILTER
Figure 1. AD9864 Block Diagram
Rev. 0
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