ADV7192_15 Datasheet, PDF (38/69 Pages) Analog Devices – Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs

ADV7192
registers has the effect of turning the Pedestal OFF on the equiva-
lent line when used in NTSC. A Logic 1 in any of the bits of
these registers has the effect of turning Teletext ON on the
equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
Figure 56. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8
Figure 57. Teletext Control Registers
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07–TC00)
(Address (SR4–SR0) = 1CH)
Teletext Control Register is an 8-bit-wide register. See Figure 58.
TTXREQ Falling Edge Control (TC00–TC03)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero clock cycles to a maximum of 15
clock cycles. This controls the active window for Teletext data.
Increasing this value reduces the amount of Teletext bits below the
default of 360. If Bits TC00–TC03 are 00Hex when Bits TC04–
TC07 are changed then the falling edge of TTREQ will track that
of the rising edge (i.e., the time between the falling and rising
edge remains constant).
PCLK = clock cycle at 27 MHz.
TTXREQ Rising Edge Control (TC04–TC07)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero clock cycles to a maximum of 15
clock cycles.
PCLK = clock cycle at 27 MHz.
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TTXREQ
RISING EDGE CONTROL
TC07 TC06 TC05 TC04
0 0 0 0 0 PCLK
0 0 0 1 1 PCLK
'' '' '' '' '' PCLK
1 1 1 0 14 PCLK
1 1 1 1 15 PCLK
TTXREQ
FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0 0 0 0 0 PCLK
0 0 0 1 1 PCLK
'' '' '' '' '' PCLK
1 1 1 0 14 PCLK
1 1 1 1 15 PCLK
Figure 58. Teletext Control Register
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address (SR4–SR0) = 19H)
CGMS_WSS register 0 is an 8-bit-wide register. Figure 59 shows
the operations under control of this register.
C/W0 BIT DESCRIPTION
CGMS Data Bits (C/W00–C/W03)
These four data bits are the final four bits of CGMS data out-
put stream. Note it is CGMS data ONLY in these bit positions,
i.e., WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (1), the last six bits of the CGMS data,
i.e., the CRC check sequence, is internally calculated by the
ADV7192. If this bit is disabled (0) the CRC values in the reg-
ister are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (1), CGMS is enabled for odd fields. Note
this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (1), CGMS is enabled for even fields. Note
this is only valid in NTSC mode.
WSS Control (C/W07)
When this bit is set (1), wide screen signalling is enabled. Note
this is only valid in PAL mode.
CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)
(Address (SR4–SR0) = 1AH)
CGMS_WSS register 1 is an 8-bit-wide register. Figure 60 shows
the operations under control of this register.
C/W1 BIT DESCRIPTION
CGMS/WSS Data (C/W10–C/W15)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these bits
are WSS data.
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
WSS CONTROL
C/W07
0 DISABLE
1 ENABLE
CGMS ODD FIELD
CONTROL
C/W05
0 DISABLE
1 ENABLE
C/W03 – C/W00
CGMS DATA BITS
CGMS EVEN FIELD
CONTROL
C/W06
0 DISABLE
1 ENABLE
CGMS CRC CHECK
CONTROL
C/W04
0 DISABLE
1 ENABLE
Figure 59. CGMS_WSS Register 0
C/W00
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REV. A