ADV7192_15 Datasheet, PDF(32/69 Page) Analog Devices – Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs

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ADV7192_15 Datasheet, PDF (32/69 Pages) Analog Devices – Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs

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ADV7192

MODE REGISTER 3

MR3 (MR37âMR30)

(Address (SR4âSR0) = 03H)

Mode Register 3 is an 8-bit-wide register. Figure 42 shows the

various operations under the control of Mode Register 3.

MR3 BIT DESCRIPTION

Revision Code (MR30âMR31)

This bit is read only and indicates the revision of the device.

VBI Open (MR32)

This bit determines whether or not data in the Vertical Blanking

Interval (VBI) is output to the analog outputs or blanked. Note

that this condition is also valid in Timing Slave Mode 0. For

further information see Vertical Blanking Data Insertion and

BLANK Input section.

Teletext Enable (MR33)

This bit must be set to 1 to enable teletext data insertion on the

TTX pin. Note: TTX functionality is shared with VSO and

CLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTX

Input/CLAMPâVSO Output (MR76) have to be set accordingly.

Teletext Bit Request Mode Control (MR34)

This bit enables switching of the teletext request signal from a

continuous high signal (MR34 = 0) to a bitwise request signal

(MR34 = 1).

Closed Captioning Field Selection (MR35âMR36)

These bits control the ï¬elds that closed captioning data is dis-

played on, closed captioning information can be displayed on

an odd ï¬eld, even ï¬eld or both ï¬elds.

Reserved (MR37)

A Logic 0 must be written to this bit.

MODE REGISTER 4

MR4 (MR47âMR40)

(Address (SR4âSR0) = 04H)

Mode Register 4 is an 8-bit-wide register. Figure 43 shows the

various operations under the control of Mode Register 4.

MR4 BIT DESCRIPTION

VSYNC_3H Control (MR40)

When this bit is enabled (1) in Slave Mode, it is possible to

drive the VSYNC input low for 2.5 lines in PAL mode and

three lines in NTSC mode. When this bit is enabled in Master

Mode the ADV7192 outputs an active low VSYNC signal for three

lines in NTSC mode and 2.5 lines in PAL mode.

Genlock Control (MR41âMR42)

These bits control the Genlock feature and timing reset of the

ADV7192. Setting MR41 and MR42 to Logic 0 disables the

SCRESET/RTC/TR pin and allows the ADV7192 to operate

in normal mode.

1. By setting MR41 to zero and MR42 to one, a timing reset is

applied, resetting the horizontal and vertical counters. This

has the effect of resetting the Field Count to Field 0.

If the SCRESET/RTC/TR pin is held high, the counters

will remain reset. Once the pin is released the counters will

commence counting again. For correct counter reset, the

SCRESET/RTC/TR pin has to remain high for at least

37 ns (one clock cycle at 27 MHz).

2. If MR41 is set to one and MR42 is set to zero, the SCRESET/

RTC/TR pin is conï¬gured as a subcarrier reset input and

the subcarrier phase will reset to Field 0 whenever a low-to-

high transition is detected on the SCRESET/RTC/TR pin

(SCH phase resets at the start of the next ï¬eld).

3. If MR41 is set to one and MR42 is set to one, the SCRESET/

RTC/TR pin is conï¬gured as a real time control input and

the ADV7192 can be used to lock to an external video source

working in RTC mode. See Real-Time Control, Subcarrier

Reset and Timing Reset section.

Active Video Line Duration (MR43)

This bit switches between two active video line durations. A zero

selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one

selects ITU-R BT. 470 standard for active video duration (710

pixels NTSC, 702 pixels PAL).

Chrominance Control (MR44)

This bit enables the color information to be switched on and off

the chroma, composite and color component outputs.

Burst Control (MR45)

This bit enables the color burst to be switched on and off the

chroma and composite outputs.

Color Bar Control (MR46)

This bit can be used to generate and output an internal color

bar test pattern. The color bar conï¬guration is 100/7.5/75/7.5

for NTSC and 100/0/75/0 for PAL. It is important to note that

when color bars are enabled the ADV7192 is conï¬gured in a

Master Timing mode. The output pins VSYNC, HSYNC and

BLANK are three-state during color bar mode.

Interlaced Mode Control (MR47)

This bit is used to setup the output to interlaced or noninter-

laced mode.

MR37

MR36

MR35

MR34

MR33

MR32

MR37

ZERO MUST BE

WRITTEN TO

THIS BIT

TTX BIT REQUEST

MODE CONTROL

MR34

0 DISABLE

1 ENABLE

VBI OPEN

MR32

0 DISABLE

1 ENABLE

CLOSED CAPTIONING

FIELD SELECTION

MR36 MR35

NO DATA OUT

ODD FIELD ONLY

EVEN FIELD ONLY

DATA OUT

(BOTH FIELDS)

TELETEXT

ENABLE

MR33

0 DISABLE

1 ENABLE

Figure 42. Mode Register 3, MR3

â32â

MR31

MR30

MR31 MR30

RESERVED FOR

REVISION CODE

REV. A

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