AD9991_15 Datasheet, PDF (38/60 Pages) Analog Devices – 10-Bit CCD Signal Processor with Precision Timing Generator

AD9991
Register Address Banks 1 and 2
The AD9991 address space is divided into two different regis-
ter banks, referred to as Register Bank 1 and Register Bank 2.
Figure 41 illustrates how the two banks are divided. Register
Bank 1 contains the registers for the AFE, miscellaneous func-
tions, VD/HD parameters, timing core, CLPOB masking, VSG
patterns, and shutter functions. Register Bank 2 contains all
of the information for the V-pattern groups, V-sequences, and
field information.
When writing to the AD9991, address 0x7F is used to specify
which address bank is being written to. To write to Bank 1, the
LSB of address 0x7F should be set to 0; to write to Bank 2, the
LSB of address 0x7F should be set to 1.
Note that Register Bank 1 contains many unused addresses. Any
undefined addresses between address 0x00 and 0x7F are consid-
ered don’t cares, and it is acceptable if these addresses are filled
in with all 0s during a continuous register write operation. How-
ever, the undefined addresses above 0x7F must not be written to,
or the AD9991 may not operate properly.
ADDR 0x00
ADDR 0x10
ADDR 0x20
ADDR 0x30
ADDR 0x40
ADDR 0x50
ADDR 0x60
ADDR 0x7F
ADDR 0x8F
ADDR 0xFF
REGISTER BANK 1
AFE REGISTERS
MISCELLANEOUS REGISTERS
VD/HD REGISTERS
TIMING CORE REGISTERS
CLPOB MASK REGISTERS
VSG PATTERN REGISTERS
SHUTTER REGISTERS
SWITCH TO REGISTER BANK 2
INVALID—DO NOT ACCESS
ADDR 0x00
ADDR 0x7E
ADDR 0x7F
ADDR 0x80
ADDR 0xCF
ADDR 0xD0
ADDR 0xFF
REGISTER BANK 2
VPAT0–VPAT9 REGISTERS
SWITCH TO REGISTER BANK 1
VSEQ0–VSEQ9 REGISTERS
FIELD 0–FIELD 5 REGISTERS
WRITE TO ADDRESS 0x7F TO SWITCH REGISTER BANKS
Figure 41. Layout of Internal Register Banks 1 and 2
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