AD7183 Datasheet, PDF (38/40 Pages) Analog Devices – Advanced Video Decoder with 10-Bit ADC and Component Input Support

ADV7183
AVSS DVSS
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AVDD
33␮F
FERRITE
BEAD
10␮F
AVSS
DVDD
33␮F
FERRITE
BEAD
AVSS
10␮F
DVSS
DVSS
100nF
100nF
100nF
100nF
100nF
100nF
INPUT
SWITCH OVER
AVSS AVSS AVSS AVSS AVSS AVSS
0.1␮F
0.1␮F _10␮F
0.1␮F
0.1␮F
0.01␮F
AVSS
AVSS
POWER SUPPLY DECOUPLING
FOR EACH POWER PIN
DVDDIO DVDD AVDD
AIN1
AVSS1
AIN2
AVSS2
AIN3
AVSS3
AIN4
AVSS4
AIN5
AVSS5
AIN6
AVSS6
ISO
CAP Y1
CAP Y2
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
GPO0
GPO1
GPO2
GPO3
0.1␮F
0.01␮F
DVSS
DVSS
MULTIFORMAT
PIXEL PORT*
POWER SUPPLY DECOUPLING
FOR EACH POWER PIN
0.1␮F
DVDD
AVSS AVSS
0.1␮F
0.1␮F _10␮F
0.1␮F
AVSS AVSS
10␮F 0.1␮F
AVSS
CAP C1
CAP C2
CML
REFOUT
LLC
LLC2
LLCREF
AEF
AFF
RD
OE
DV
GL/QCLK/HFF
PWRDN
HS/RESET
VS/RESET
FIELD
27MHz OUTPUT CLOCK
13.5MHz OUTPUT CLOCK
CLOCK REFERENCE O/P
ALMOST EMPTY FIFO O/P
ALMOST FULL FIFO O/P
READ SIGNAL I/P
OUTPUT ENABLE I/P
DATA VALID O/P
GL/QCLK/HFF O/P
FIFO MANAGEMENT
SIGNALS ONLY USED
IN FIFO MODE;
USE LLC AND GENLOCK
FOR NON-FIFO MODE
POWER-DOWN INPUT
HS/RESET O/P
VS/RESET O/P
FIELD O/P
DVSS
DVDD DVDD
33␮F
27MHz
DVSS
33␮F
DVSS
XTAL
XTAL1
ELPF
5.6k⍀
2nF
68pF
AVDD
2k⍀
I²C INTERFACE
CONTROL LINE
I²C INTERFACE
CONTROL LINE
2k⍀
100R
100R
ALSB
SCLK
SDA
4.7k⍀
DVDD
100nF
RESET DVSS
RESET
*P15–P8: 8-BIT CCIR656 PIXEL DATA @ 27MHz
P7–P0: Cb AND Cr 16-BIT CCIR656 PIXEL DATA @ 13.5MHz
P15–P8: Y1 AND Y2 16-BIT CCIR656 PIXEL DATA @ 13.5MHz
Figure 30. Recommended Analog Circuit Layout
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