AD9983A Datasheet, PDF (37/44 Pages) Analog Devices – High Performance 8-Bit Display Interface

Preliminary Technical Data
SYNC PROCESSING
0x20—Bit[2] PLL Sync Filter
This bit selects which signal the PLL uses. It can select between
either raw Hsync or SOG or filtered versions. The filtering of
the Hsync and SOG can eliminate nearly all extraneous
transitions, which have traditionally caused PLL disruption.
The power-up default setting is 0.
Table 60. PLL Sync Filter Enable
Select
Result
0
PLL uses raw Hsync or SOG inputs
1
PLL uses filtered Hsync or SOG inputs
0x20—Bit[1] Sync Processing Input Source
This bit selects whether the sync processor uses a raw sync or a
regenerated sync for the following functions: coast, H/V count,
field detection and Vsync duration counts. Using the
regenerated sync is recommended.
Table 61. SP Filter Enable
Select Result
0
Sync processing uses raw Hsync or SOG
1
Sync processing uses the internally regenerated Hsync
0x21—Bits[7:0]
Must be set to default
0x22—Bits[7:0]
Must be set to default
0x23—Bits[7:0] Sync Filter Window Width
This 8-bit register sets the window of time for the regenerated
Hsync leading edge (in 25 ns steps) and that sync pulses are
allowed to pass through. Therefore with the default value of 10,
the window width is ±250 ns. The goal is to set the window
width so that extraneous pulses are rejected. (see the Sync
Processing section). As in the sync separator threshold, the
25 ns multiplier value is somewhat variable. The maximum
variability over all operating conditions is ±20% (20 ns to 30 ns).
DETECTION STATUS
0x24—Bit[7] HSYNC0 Detection Bit
This bit is used to indicate when activity is detected on the
HSYNC0 input pin. If Hsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = HSYNC0 not active. 1 = HSYNC0
is active.
Table 62. HSYNC0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
AD9983A
0x24—Bit[6] HSYNC1 Detection Bit
This bit is used to indicate when activity is detected on the
HSYNC1 input pin. If Hsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = HSYNC1 not active. 1 = HSYNC1
is active.
Table 63. HSYNC1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24—Bit[5] VSYNC0 Detection Bit
This bit is used to indicate when activity is detected on the
VSYNC0 input pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = VSYNC0 not active. 1 = VSYNC0
is active.
Table 64. VSYNC0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24—Bit[4] VSYNC1 Detection Bit
This bit is used to indicate when activity is detected on the
VSYNC1 input pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = VSYNC1 not active. 1 = VSYNC1
is active.
Table 65. VSYNC1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24—Bit[3] SOGIN0 Detection Bit
This bit is used to indicate when activity is detected on the
SOGIN0 input pin. If SOG is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = SOGIN0 not active. 1 = SOGIN0
is active.
Table 66. SOGIN0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
Rev. PrA | Page 37 of 44