AD9983A Datasheet, PDF (1/44 Pages) Analog Devices – High Performance 8-Bit Display Interface

Preliminary Technical Data
FEATURES
8-bit analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green pulse filter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9983A is a complete 8-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p as well as graphics resolutions up to UXGA
(1600 x 1200 at 60 Hz).
The AD9983A includes a 170 MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9983A on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of sync input. A 32-step
High Performance
8-Bit Display Interface
AD9983A
FUNCTIONAL BLOCK DIAGRAM
AD9983A
8
AUTO OFFSET
Pr/RED_IN1
Pr/RED_IN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
8-BIT
ADC
8
AUTO OFFSET
Y/GREEN_IN1
Y/GREEN_IN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
8-BIT
ADC
8
AUTO OFFSET
Pb/BLUE_IN1
Pb/BLUE_IN0
2:1
MUX
CLAMP
AUTO GAIN
PGA
8-BIT
ADC
8
Cb/Cr/RED_OUT
8
Y/GREEN_OUT
8
Cb/BLUE_OUT
HSYNC1
HSYNC0
VSYNC0
VSYNC1
SOGIN1
SOGIN0
EXTCK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
Figure 1.
DATACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFLO
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The auto channel-
to-channel gain matching feature can be enabled to minimize
any gain mismatches between the three channels.
The AD9983A also offers full sync processing for composite
sync and sync-on-green applications. A clamp signal is
generated internally or may be provided by the user through the
CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9983A is
provided in a space-saving 80-lead, Pb-free, LQFP surface-
mount plastic package or a 64-lead LFCSP package, and is
specified over the 0°C to 70°C temperature range.
Rev. PrA
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