AD9255BCPZRL7-80 Datasheet, PDF (37/44 Pages) Analog Devices – 14-Bit, 125 MSPS/105 MSPS/80 MSPS

Data Sheet
AD9255
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr. Register
(Hex) Name
Bit 7 (MSB)
Chip Configuration Registers
0x00 SPI port
0
configuration
Bit 6
LSB first
0x01 Chip ID
0x02 Chip grade
Open
Open
Transfer Register
0xFF Transfer
Open
Open
ADC Functions Registers
0x08 Power
1
modes
Open
0x09 Global clock Open
Open
0x0B Clock divide Open
(global)
Open
0x0D Test mode
Open
Open
0x0E BIST enable Open
Open
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Default
Value Default Notes/
Bit 0 (LSB) (Hex) Comments
Soft reset
1
1
Soft reset LSB
0
first
8-Bit Chip ID[7:0], AD9255 = 0x65 (default)
Speed grade ID
Open Open
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Open Open
0x18
0x65
The nibbles are
mirrored so
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
Speed grade ID
used to
differentiate
devices; read
only
Open
Open
Open Open
Open Transfer 0x00
Synchronously
transfers data
from the
master shift
register to the
slave
External power-
down pin
function
0 = power-
down
1 = standby
Open
Open
Reset PN23
generator
Open
Open
Open
Open
Reset PN9
generator
Open
Open
Open
Open
Open
Open
Open
Internal
power-down
mode
00 = normal
operation
01 = full power-
down
10 = standby
11 = normal
operation
Open
Open
Duty
cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN 23 sequence
110 = PN 9 sequence
111 = one/zero word toggle
Reset BIST Open BIST
sequence
enable
0x80
0x01
0x00
0x00
0x04
Determines
various generic
modes of chip
operation
Clock divide
values other
than 000
automatically
cause the duty
stabilizer to
become active.
When this
register is set,
the test data is
placed on the
output pins in
place of normal
data
Rev. C | Page 37 of 44