ADSP-21992_07 Datasheet, PDF (35/60 Pages) Analog Devices – Mixed-Signal DSP Controller with CAN

ADSP-21992
External Port Write Cycle Timing
Table 20 and Figure 10 describe external port write operations.
The external port lets systems extend read/write accesses in
three ways: wait states, ACK input, and combined wait states
and ACK. To add waits with ACK, the DSP must see ACK low
Table 20. External Port Write Cycle Timing
at the rising edge of EMI clock. ACK low causes the DSP to wait,
and the DSP requires two EMI clock cycles after ACK goes high
to finish the access. For more information, see the External Port
chapter in the ADSP-2199x DSP Hardware Reference.
Parameter
Timing Requirements^{1, 2}
t_AKW
ACK Strobe Pulse Width
t_DWSAK
ACK Delay from XMS Low
Switching Characteristics
t_CSWS
Chip Select Asserted to WR Asserted Delay
t_AWS
Address Valid to WR Setup and Delay
t_WSCS
WR Deasserted to Chip Select Deasserted
t_WSA
WR Deasserted to Address Invalid
t_WW
WR Strobe Pulse Width
t_CDA
WR to Data Enable Access Delay
t_CDD
WR to Data Disable Access Delay
t_DSW
t_DHW
t_DHW
Data Valid to WR Deasserted Setup
WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 5}
WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 6}
t_WWR
WR Deasserted to WR, RD Asserted
1 _{tEMICLK is the external memory interface clock period. tHCLK is the peripheral clock period.}
2 _{These are timing parameters that are based on worst-case operating conditions.}
3 _{W = (number of wait states specified in wait register) ؋ tEMICLK.}
4 _{Write hold cycle memory select control registers (MS 3 CTL).}
5 _{Write wait state count (E_WHC) = 0}
6 _{Write wait state count (E_WHC) = 1}
Min
Max
Unit
12.5
ns
0.5t_EMICLK – 1
ns
0.5t_EMICLK – 4
0.5t_EMICLK – 3
0.5t_EMICLK – 4
0.5t_EMICLK – 3
t_EMICLK –2 + W³
0.5t_EMICLK – 3
t_EMICLK + 1 + W³
3.4
t_EMICLK+ 3.4
t_HCLK
ns
ns
ns
ns
ns
0
ns
0.5t_EMICLK + 4
ns
t_EMICLK + 7 + W³
ns
ns
ns
ns
Rev. A | Page 35 of 60 | August 2007