ADSP-21992_07 Datasheet, PDF (3/60 Pages) Analog Devices – Mixed-Signal DSP Controller with CAN

GENERAL DESCRIPTION
The ADSP-21992 is a mixed-signal DSP controller based on the
ADSP-2199x DSP core, suitable for a variety of high perfor-
mance industrial motor control and signal processing
applications that require the combination of a high performance
DSP and the mixed-signal integration of embedded control
peripherals, such as analog-to-digital conversion with commu-
nications interfaces such as CAN. Target applications include
industrial motor drives, uninterruptible power supplies, optical
networking control, data acquisition systems, test and measure-
ment Systems, and portable instrumentation.
The ADSP-21992 integrates the fixed-point ADSP-2199x fam-
ily-based architecture with a serial port, an SPI-compatible port,
a DMA controller, three programmable timers, general-purpose
programmable flag pins, extensive interrupt capabilities, on-
chip program and data memory spaces, and a complete set of
embedded control peripherals that permits fast motor control
and signal processing in a highly integrated environment.
The ADSP-21992 architecture is code compatible with previous
ADSP-217x-based ADMCxxx products. Although the architec-
tures are compatible, the ADSP-21992, with ADSP-2199x
architecture, has a number of enhancements over earlier archi-
tectures. The enhancements to computational units, data
address generators, and program sequencer make the
ADSP-21992 more flexible and easier to program than the pre-
vious ADSP-21xx embedded DSPs.
Indirect addressing options provide addressing flexibility—pre-
modify with no update, pre- and post-modify by an immediate
8-bit, twos complement value and base address registers for eas-
ier implementation of circular buffering.
The ADSP-21992 integrates 48K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21992 operates with a 6.25 ns instruction cycle time for a
160 MHz CCLK, with a 6.67 ns instruction cycle time for a
150 MHz CCLK, and with a 10.0 ns instruction cycle time for a
100 MHz CCLK. All instructions, except two multiword
instructions, execute in a single DSP cycle.
The flexible architecture and comprehensive instruction set of
the ADSP-21992 support multiple operations in parallel. For
example, in one processor cycle, the ADSP-21992 can:
• Generate an address for the next instruction fetch.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computational operation.
These operations take place while the processor continues to:
• Receive and transmit data through the serial port.
• Receive or transmit data over the SPI port.
• Access external memory through the external memory
interface.
ADSP-21992
• Decrement the timers.
• Operate the embedded control peripherals (ADC, PWM,
EIU, etc.).
DSP CORE ARCHITECTURE
• 6.25 ns instruction cycle time (internal), for up to
160 MIPS sustained performance (6.67 ns instruction cycle
time for 150 MIPS sustained performance and 10.0 ns
instruction cycle time for 100 MIPS sustained
performance).
• ADSP-218x family code compatible with the same easy to
use algebraic syntax.
• Single cycle instruction execution.
• Up to 1M words of addressable memory space with 24 bits
of addressing width.
• Dual-purpose program memory for both instruction and
data storage.
• Fully transparent instruction cache allows dual operand
fetches in every instruction cycle.
• Unified memory space permits flexible address generation,
using two independent DAG units.
• Independent ALU, multiplier/accumulator, and barrel
shifter computational units with dual 40-bit accumulators.
• Single cycle context switch between two sets of computa-
tional and DAG registers.
• Parallel execution of computation and memory
instructions.
• Pipelined architecture supports efficient code execution at
speeds up to 160 MIPS.
• Register file computations with all nonconditional, non-
parallel computational instructions.
• Powerful program sequencer provides zero overhead loop-
ing and conditional instruction execution.
• Architectural enhancements for compiled C code
efficiency.
• Architecture enhancements beyond ADSP-218x family are
supported with instruction set extensions for added regis-
ters, ports, and peripherals.
The clock generator module of the ADSP-21992 includes clock
control logic that allows the user to select and change the main
clock frequency. The module generates two output clocks: the
DSP core clock, CCLK; and the peripheral clock, HCLK. CCLK
can sustain clock values of up to 160 MHz, while HCLK can be
equal to CCLK or CCLK/2 for values up to a maximum 80 MHz
peripheral clock at the 160 MHz CCLK rate.
The ADSP-21992 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single word instruction can be executed in a
single processor cycle. The ADSP-21992 assembly language uses
Rev. A | Page 3 of 60 | August 2007