ADSP-TS101S Datasheet, PDF (34/44 Pages) Analog Devices – Embedded Processor

ADSP-TS101S
25
STRENGTH 4
(V_{DD_IO} = 3.3V)
20
15
10
RISE TIME
y = 0.1071x + 0.9877
5
FALL TIME
y = 0.0798x + 1.0743
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 29. Typical Output Rise and Fall Time (10%–90%,
V_{DD_IO} = 3.3 V) vs. Load Capacitance at Strength 4
25
STRENGTH 7
(V_{DD_IO} = 3.3V)
20
15
10
RISE TIME
y = 0.0907x + 1.0071
5
FALL TIME
y = 0.09x + 0.3134
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 32. Typical Output Rise and Fall Time (10%–90%,
V_{DD_IO} = 3.3 V) vs. Load Capacitance at Strength 7
25
STRENGTH 5
(V_{DD_IO} = 3.3V)
20
15
10
RISE TIME
y = 0.1001x + 0.7763
5
FALL TIME
y = 0.0793x + 0.8691
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 30. Typical Output Rise and Fall Time (10%–90%,
V_{DD_IO} = 3.3 V) vs. Load Capacitance at Strength 5
25
STRENGTH 6
(V_{DD_IO} = 3.3V)
20
15
15
STRENGTH 0-7
0
(V_{DD_IO} = 3.3V)
10
1
2
3
4
5
5
6
7
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 33. Typical Output Valid (V_{DD_IO} = 3.3 V) vs. Load
Capacitance at Max Case Temperature and Strength 0–7¹
1 _{The line equations for the output valid versus load capacitance are:}
Strength 0: y = 0.0956x + 3.5662
Strength 1: y = 0.0523x + 3.2144
Strength 2: y = 0.0433x + 3.1319
Strength 3: y = 0.0391x + 2.9675
Strength 4: y = 0.0393x + 2.7653
Strength 5: y = 0.0373x + 2.6515
Strength 6: y = 0.0379x + 2.1206
Strength 7: y = 0.0399x + 1.9080
10
RISE TIME
y = 0.0946x + 1.2187
5
FALL TIME
y = 0.0906x + 0.4597
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 31. Typical Output Rise and Fall Time (10%–90%,
V_{DD_IO} = 3.3 V) vs. Load Capacitance at Strength 6
–34–
REV. A