ADSP-TS101S Datasheet, PDF (1/44 Pages) Analog Devices – Embedded Processor

a
T
Embedded Processor
ADSP-TS101S
KEY FEATURES
300 MHz, 3.3 ns Instruction Cycle Rate
6M Bits of Internal—On-Chip—SRAM Memory
19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm
(625-Ball) PBGA Package
Dual Computation Blocks—Each Containing an ALU, a
Multiplier, a Shifter, and a Register File
Dual Integer ALUs, Providing Data Addressing and
Pointer Manipulation
Integrated I/O Includes 14 Channel DMA Controller,
External Port, Four Link Ports, SDRAM Controller,
Programmable Flag Pins, Two Timers, and Timer
Expired Pin for System Integration
1149.1 IEEE Compliant JTAG Test Access Port for
On-Chip Emulation
On-Chip Arbitration for Glueless Multiprocessing with
up to Eight TigerSHARC Processors on a Bus
KEY BENEFITS
Provides High Performance Static Superscalar DSP
Operations, Optimized for Telecommunications
Infrastructure and Other Large, Demanding
Multiprocessor DSP Applications
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table 1 and Table 2)
Supports Low Overhead DMA Transfers Between
Internal Memory, External Memory, Memory-Mapped
Peripherals, Link Ports, Host Processors, and Other
(Multiprocessor) DSPs
Eases DSP Programming Through Extremely Flexible
Instruction Set and High Level Language Friendly DSP
Architecture
Enables Scalable Multiprocessing Systems with Low
Communications Overhead
FUNCTIONAL BLOCK DIAGRAM
COMPUTATIONAL BLOCKS
SHIFTER
ALU
MULTIPLIER
X
REGISTER
FILE
32x32
128 128
DAB
DAB
128 128
Y
REGISTER
FILE
32x32
MULTIPLIER
ALU
SHIFTER
PROGRAM SEQUENCER
PC BTB IRQ
ADDR
IAB
FETCH
DATA ADDRESS GENERATION
INTEGER ³²
J ALU
32 _INTEGER
K ALU
32x32
32x32
32
128
32
128
32
128
I/O PROCESSOR
DMA
CONTROLLER
CONTROL/
STATUS/
TCBs
DMA ADDRESS
DMA DATA
INTERNAL MEMORY
MEMORY MEMORY MEMORY
M0
M1
M2
64Kx32 64Kx32 64Kx32
A DA DA D
6
JTAG PORT
SDRAM CONTROLLER
32 256
M0 ADDR
M0 DATA
M1 ADDR
M1 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
HOST INTERFACE
INPUT FIFO
32
ADDR
64
OUTPUT BUFFER
DATA
M2 ADDR
M2 DATA
I/O ADDRESS 32
OUTPUT FIFO
CLUSTER BUS
ARBITER
CNTRL
3
LINK PORT
CONTROLLER
L0
8
3
256
LINK DATA
L1
8
LINK
PORTS
3
CONTROL/
STATUS/
BUFFERS
L2
8
3
L3
8
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:[phone]
www.analog.com
Fax:[phone]
© 2003 Analog Devices, Inc. All rights reserved.