ADSP-2196M_15 Datasheet, PDF (34/68 Pages) Analog Devices – DSP Microcomputer

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ADSP-2196
For current information contact Analog Devices at 800/262-5643
September 2001
Host Port ALE Mode Write Cycle Timing
Table 14 and Figure 17 describe host port write operations in Address Latch Enable (ALE) mode. For more information
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 14. Host Port ALE Mode Write Cycle Timing
Parameter Description
Min
Max
Unit
Switching Characteristics
t_WHKS
HWR asserted to HACK asserted (setup, ACK Mode)
0.6
t_WHKH
HWR de-asserted to HACK de-asserted (hold, ACK Mode)
t_WHS
HWR asserted to HACK asserted (setup, Ready Mode)
t_WHH
HWR asserted to HACK de-asserted (hold, Ready Mode)
Timing Requirements
0.6 + t_NH¹
ns
2
ns
0.6
ns
2+ t_NH¹
ns
t_CSAL
HCMS or HCIOMS asserted to HALE asserted
0
ns
t_ALPW
HALE asserted pulsewidth
4
ns
t_ALCSW
HALE de-asserted to HCMS or HCIOMS de-asserted
1
ns
t_WCSW
HWR de-asserted to HCMS or HCIOMS de-asserted
1
ns
t_ALW
HALE de-asserted to HWR asserted
1
ns
t_WCS
HWR de-asserted (after last byte) to HCMS or
1
ns
HCIOMS de-asserted (ready for next write)
t_HKWD
HACK asserted to HWR de-asserted (hold, ACK Mode)
1.5
ns
t_AALS
Address valid to HALE de-asserted (setup)
4
ns
t_ALAH
HALE de-asserted to address invalid (hold)
1.5
ns
t_DWS
Data valid to HWR de-asserted (setup)
4
ns
t_WDH
HWR de-asserted to data invalid (hold)
1
ns
1_{tNH are peripheral bus latencies (n؋tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at}
the same time.
34
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.