ADSP-2196M_15 Datasheet, PDF (25/68 Pages) Analog Devices – DSP Microcomputer

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September 2001 ^{For current information contact Analog Devices at 800/262-5643}
ADSP-2196
Clock In and Clock Out Cycle Timing
Table 8 and Figure 11 describe clock and reset operations. Per V_DDINTInternal (Core) Supply Voltage, –0.3 to 3.0 V on
page 24, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz.
Table 8. Clock In and Clock Out Cycle Timing
Parameter
Description
Min
Max
Unit
Switching Characteristic
t_CKOD
t_CKO
CLKOUT delay from CLKIN
CLKOUT period¹
0
5.8
ns
10
ns
Timing Requirements
t_CK
CLKIN period^2,3
6.25
200
ns
t_CKL
CLKIN low pulse
2.2
ns
t_CKH
CLKIN high pulse
2.2
ns
t_WRST
RESET asserted pulsewidth low
200t_CLKOUT
ns
t_MSLS
MSELx/BYPASS stable before RESET asserted setup
160
µs
t_MSLH
MSELx/BYPASS stable after RESET de-asserted hold 1000
ns
1_{Figure 11 shows a ؋2 ratio between CLKOUT = 2؋CLKIN (or tHCLK = 2؋tCCLK), but the ratio has many programmable options. For more information}
see the System Design chapter of the ADSP-219x/2191 DSP Hardware Reference.
2_{In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), tCK=tCCLK.}
3_{In bypass mode, tCK=tCCLK.}
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Figure 11. Clock In and Clock Out Cycle Timing
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
25
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.