AD9635 Datasheet, PDF (34/36 Pages) Analog Devices – Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter

AD9635
Data Sheet
Bits[3:0]—Output Clock Phase Adjust
See Table 19 for details.
Table 19. Output Clock Phase Adjust Options
Output Clock (DCO),
DCO Phase Adjustment (Degrees
Phase Adjust, Bits[3:0] Relative to D0x±/D1x± Edge)
0000
0
0001
60
0010
120
0011 (Default)
180
0100
240
0101
300
0110
360
0111
420
1000
480
1001
540
1010
600
1011
660
Serial Output Data Control (Register 0x21)
The serial output data control register is used to program the
AD9635 in various output data modes, depending on the data
capture solution. Table 20 describes the various serialization
options available in the AD9635.
Resolution/Sample Rate Override (Register 0x100)
This register allows the user to downgrade the resolution and/or
the maximum sample rate (for lower power) in applications that do
not require full resolution and/or sample rate. Settings in this
register are not initialized until Bit 0 of the transfer register
(Register 0xFF) is written high.
Bits[2:0] do not affect the sample rate; they affect the maximum
sample rate capability of the ADC.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM generator.
This feature is used when applying an input common mode
voltage from an external source.
Bits[2:0]—Open
Table 20. SPI Register Options
Serialization Options Selected
Register 0x21 Serial Output Number
Contents
of Bits (SONB)
Frame Mode
Serial Data Mode
0x32
12-bit
1×
DDR two-lane bytewise
0x22
12-bit
1×
DDR two-lane bitwise
0x12
12-bit
1×
SDR two-lane bytewise
0x02
12-bit
1×
SDR two-lane bitwise
0x36
12-bit
2×
DDR two-lane bytewise
0x26
12-bit
2×
DDR two-lane bitwise
0x16
12-bit
2×
SDR two-lane bytewise
0x06
12-bit
2×
SDR two-lane bitwise
0x42
12-bit
1×
DDR one-lane wordwise
0x33
10-bit
1×
DDR two-lane bytewise
0x23
10-bit
1×
DDR two-lane bitwise
0x13
10-bit
1×
SDR two-lane bytewise
0x03
10-bit
1×
SDR two-lane bitwise
0x37
10-bit
2×
DDR two-lane bytewise
0x27
10-bit
2×
DDR two-lane bitwise
0x17
10-bit
2×
SDR two-lane bytewise
0x07
10-bit
2×
SDR two-lane bitwise
0x43
10-bit
1×
DDR one-lane wordwise
DCO Multiplier
3 × fS
3 × fS
6 × fS
6 × fS
3 × fS
3 × fS
6 × fS
6 × fS
6 × fS
2.5 × fS
2.5 × fS
5 × fS
5 × fS
2.5 × fS
2.5 × fS
5 × fS
5 × fS
5 × fS
Timing Diagram
See Figure 2 (default setting)
See Figure 2
See Figure 2
See Figure 2
See Figure 4
See Figure 4
See Figure 4
See Figure 4
See Figure 6
See Figure 3
See Figure 3
See Figure 3
See Figure 3
See Figure 5
See Figure 5
See Figure 5
See Figure 5
See Figure 7
Rev. B | Page 34 of 36