AD9635 Datasheet, PDF (1/36 Pages) Analog Devices – Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter

Data Sheet
Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS
1.8 V Analog-to-Digital Converter
AD9635
FEATURES
1.8 V supply operation
Low power: 115 mW per channel at 125 MSPS with scalable
power options
SNR = 71 dBFS (to Nyquist)
SFDR = 93 dBc at 70 MHz
DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging and ultrasound
Radar/LIDAR
GENERAL DESCRIPTION
The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to-
digital converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
Rev. B
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VINA+
VINA–
VCM
VINB+
VINB–
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD9635
12
12-BIT PIPELINE
ADC
12
12
12-BIT PIPELINE
ADC
12
REFERENCE
D0A+
D0A–
D1A+
D1A–
D0B+
D0B–
D1B+
D1B–
DCO+
DCO–
FCO+
FCO–
SERIAL PORT
INTERFACE
1 TO 8
CLOCK DIVIDER
SCLK/ SDIO/ CSB
DFS PDWN
CLK+ CLK–
Figure 1.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported; the AD9635 typically consumes less
than 2 mW in the full power-down state. The ADC provides
several features designed to maximize flexibility and minimize
system cost, such as programmable output clock and data align-
ment and digital test pattern generation. The available digital
test patterns include built-in deterministic and pseudorandom
patterns, along with custom user-defined test patterns entered via
the serial port interface (SPI).
The AD9635 is available in a RoHS-compliant, 32-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Two ADCs are contained in a small, space-
saving package.
2. Low Power. The AD9635 uses 115 mW/channel at 125 MSPS
with scalable power options.
3. Pin Compatibility with the AD9645, a 14-Bit Dual ADC.
4. Ease of Use. A data clock output (DCO) operates at
frequencies of up to 500 MHz and supports double data
rate (DDR) operation.
5. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
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