ADV601 Datasheet, PDF (33/52 Pages) Analog Devices – Low Cost Multiformat Video Codec

ADV601
A2
A3
D0–D7
SYSTEM
DEPENDENT
ASIC
BE0
BE1
BE2
BE3
CS
RD
WR
TFS
RTF
ADSP-21xx ^TD
RD
SCLK
IRQ2
ADR0
A0–A8
ADR1
DQ0–DQ7
DQ8–DQ15
D0–D15
RAS
CAS
DQ16–DQ23
DQ24–DQ31
BE0
WE
BE1
BE2
BE3
CS
ADV601
RD
WR
ACK
VCLKO
RF
TF
RXD
TXD
TCLK
DIRQ
VCLK
CREF
VSYNC
HSYNC
FIELD
VDATA [2:9]
VDATA [12:19]
A0–A8
DQ1–DQ16
RAS
CAS
OE ^DRAM
(256K X 16-BIT)
WEL
WEH
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
uPD424210ALE-60
NEC
uPD42S4210ALE-60
HITACHI HM514265CJ-60
ANY DRAM USED WITH THE ADV601
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
29.50000MHz PAL
OR
24.54543MHz NTSC
26.80000MHz
XTAL
XTAL
LLC
CREF
VS _SAA7110
HREF
ODD
Y[0–7]
UV[7–0]
COMPOSITE VIDEO INPUT
Figure 15. Suggested Standalone Application Design
ADR1
ADR2
DATA0–7
DATA8-15
ADR0
ADSP-21csp01
CLKIN
IOMS
RD
WR
FLIN2
FLIN0
IRQ0
FLIN1
IOACK
THE ADSP-21csp01 INTERNAL CLOCK RATE
DOUBLE THE INPUT CLOCK
*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL
CLOCK RATE, RANGING FROM 12 TO 21MHz
ADR0
A0–A8
ADR1
D0–D15
DQ0–DQ7
DQ8–DQ15
RAS
CAS
DQ16–DQ23
DQ24–DQ31
WE
BE0
BE1
BE2
BE3
ADV601
VCLKO*
CS
RD
WR
FIFO_ERR
STATS_R
HIRQ
LCODE
ACK
FIFO_SRQ
FIFO_STP
VCLK
CREF
VSYNC
HSYNC
FIELD
VDATA [2:9]
VDATA [0:19]
A0–A8
DQ1–DQ16
RAS
CAS
OE ^DRAM
(256K X 16-BIT)
WEL
WEH
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
uPD424210ALE-60
NEC
uPD42S4210ALE-60
HITACHI HM514265CJ-60
ANY DRAM USED WITH THE ADV601
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
29.50000MHz PAL
OR
24.54543MHz NTSC
26.80000MHz
XTAL
XTAL
LLC
CREF
VS SAA7110
HREF
ODD
Y[0–7]
UV[7–0]
COMPOSITE VIDEO INPUT
Figure 16. Alternate Standalone Application Design
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