ADUC7060 Datasheet, PDF (32/108 Pages) Analog Devices – Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI

ADuC7060/ADuC7061
RESET
There are four kinds of resets: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.
The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated inTable 30.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default value: Depends on type of reset
Access:
Read and write
Function:
This 8-bit register indicates the source of the
last reset event and can be written by user code
to initiate a software reset.
RSTCLR Register
Name:
RSTCLR
Address: 0xFFFF0234
Access: Write only
Function: This 8-bit write only register clears the corres-
ponding bit in RSTSTA.
Table 29. RSTSTA/RSTCLR MMR Bit Designations
Bit
Description
7:4
Not used. These bits are not used and always
read as 0.
3
External reset.
Automatically set to 1 when an external reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
2
Software reset.
This bit is set to 1 by user code to generate a soft-
ware reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.¹
1
Watchdog timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-on reset.
Automatically set when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1 _{If the software reset bit in RSTSTA is set, any write to RSTCLR that does not}
clear this bit generates a software reset.
Table 30. Device Reset Implications
RESET
Reset
External Pins to
Default State
Kernel
Executed
POR
Yes
Yes
Watchdog Yes
Yes
Software Yes
Yes
External Pin Yes
Yes
Reset All
External MMRs
(Excluding RSTSTA)
Yes
Yes
Yes
Yes
Peripherals
Reset
Yes
Yes
Yes
Yes
Watchdog
Timer Reset
Yes
No
No
No
RAM
Valid
Yes/No
Yes
Yes
Yes
RSTSTA
(Status After
Reset Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1
Rev. B | Page 32 of 108