ADUC7060 Datasheet, PDF (30/108 Pages) Analog Devices – Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI

ADuC7060/ADuC7061
Table 24. I²C Base Address = 0xFFFF0900
Address Name
Bytes Access Type
0x0900 I2CMCON 2
R/W
0x0904 I2CMSTA 2
R
0x0908 I2CMRX 1
R
0x090C I2CMTX 1
W
0x0910 I2CMCNT0 2
R/W
Default Value
0x0000
0x0000
0x00
0x00
0x0000
0x0914 I2CMCNT1 1
R
0x00
0x0918 I2CADR0 1
R/W
0x00
0x091C I2CADR1 1
R/W
0x00
0x0924 I2CDIV
2
R/W
0x0928 I2CSCON 2
R/W
0x092C I2CSSTA 2
R/W
0x0930 I2CSRX 1
R
0x0934 I2CSTX
1
W
0x0938 I2CALT
1
R/W
0x093C I2CID0
1
R/W
0x0940 I2CID1
1
R/W
0x0944 I2CID2
1
R/W
0x0948 I2CID3
1
R/W
0x094C I2CFSTA 2
R/W
0x1F1F
0x0000
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0000
Table 25. SPI Base Address = 0xFFFF0A00
Address Name
Access
Bytes Type
0x0A00 SPISTA
4
R
0x0A04 SPIRX
1
R
0x0A08 SPITX
1
W
0x0A0C SPIDIV
1
W
0x0A10 SPICON
2
R/W
Default Value
0x00000000
0x00
0x00
0x1B
0x0000
Table 26. GPIO Base Address = 0xFFFF0D00
Address Name
Access
Bytes Type
Default Value
0x0D00 GP0CON0 4
R/W
0x00000000
0x0D04 GP1CON 4
R/W
0x00000000
0x0D08 GP2CON 4
R/W
0x00000000
0x0D20 GP0DAT 4
R/W
0x000000XX
0x0D24 GP0SET 4
W
0x000000XX
0x0D28 GP0CLR 4
W
0x000000XX
0x0D2C GP0PAR 4
R/W
0x00000000
0x0D30 GP1DAT 4
R/W
0x000000XX
0x0D34 GP1SET 4
W
0x000000XX
0x0D38 GP1CLR 4
W
0x000000XX
0x0D3C GP1PAR 4
R/W
0x00000000
0x0D40 GP2DAT 4
R/W
0x000000XX
0x0D44 GP2SET 4
W
0x000000XX
0x0D48 GP2CLR 4
W
0x000000XX
0x0D4C GP2PAR 4
R/W
0x00000000
Description
I²C master control register.
I²C master status register.
I²C master receive register.
I²C master transmit register.
I²C master read count register. Write the number of required bytes into
this register prior to reading from a slave device.
I²C master current read count register. This register contains the
number of bytes already received during a read from slave sequence.
Address byte register. Write the required slave address here prior to
communications.
Address byte register. Write the required slave address here prior to
communications. Only used in 10-bit mode.
I²C clock control register. Used to configure the SCLK frequency.
I²C slave control register.
I²C slave status register.
I²C slave receive register.
I²C slave transmit register.
I²C hardware general call recognition register.
I²C Slave ID0 register. Slave bus ID register.
I²C Slave ID1 register. Slave bus ID register.
I²C Slave ID2 register. Slave bus ID register.
I²C Slave ID3 register. Slave bus ID register.
I²C FIFO status register. Used in both master and slave modes.
Description
SPI status MMR.
SPI receive MMR.
SPI transmit MMR.
SPI baud rate select MMR.
SPI control MMR.
Description
GPIO Port 0 control MMR.
GPIO Port 1 control MMR.
GPIO Port 2 control MMR.
GPIO Port 0 data control MMR.
GPIO Port 0 data set MMR.
GPIO Port 0 data clear MMR.
GPIO Port 0 pull-up disable MMR.
GPIO Port 1 data control MMR.
GPIO Port 1 data set MMR.
GPIO Port 1 data clear MMR.
GPIO Port 1 pull-up disable MMR.
GPIO Port 2 data control MMR.
GPIO Port 2 data set MMR.
GPIO Port 2 data clear MMR.
GPIO Port 2 pull-up disable MMR.
Rev. B | Page 30 of 108