ADSP-2106X Datasheet, PDF (32/47 Pages) Analog Devices – DSP Microcomputer Family

ADSP-21061/ADSP-21061L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR_31-0, RD, WR, SW, PAGE, MS_3-0,
ACK and DMAG signals. For Paced Master mode, the data
transfer is controlled by ADDR_31-0, RD, WR, MS_3-0 and ACK
(not DMAG). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR_31-0, RD,
WR, MS_3-0, SW, PAGE, DATA_47-0 and ACK also apply.
Parameter
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
Unit
Timing Requirements:
t_SDRLC
t_SDRHC
t_WDR
t_SDATDGL
t_HDATIDG
t_DATDRH
t_DMARLL
t_DMARH
DMARx Low Setup before CLKIN¹
DMARx High Setup before CLKIN¹
DMARx Width Low (Nonsynchronous)
Data Setup after DMAGx Low²
Data Hold after DMAGx High
Data Valid after DMARx High²
DMAGx Low Edge to Low Edge
DMAGx Width High
5
5
6
2
23 + 7DT/8
6
10 + 5DT/8
16 + 7DT/8
5
ns
5
ns
6
ns
10 + 5DT/8
ns
2
ns
16 + 7DT/8
ns
23.5 + 7DT/8
ns
6
ns
Switching Characteristics:
t_DDGL
t_WDGH
t_WDGL
t_HDGC
t_DADGH
t_DDGHA
t_VDATDGH
t_DATRDGH
t_DGWRL
t_DGWRH
t_DGWRR
t_DGRDL
t_DRDGH
t_DGRDR
DMAGx Low Delay after CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay after CLKIN
Address Select Valid to DMAGx High
Address Select Hold to DMAGx High
Data Valid before DMAGx High³
Data Disable after DMAGx High⁴
WR Low before DMAGx Low
DMAGx Low before WR High
WR High before DMAGx High
RD Low before DMAGx Low
RD Low before DMAGx High
RD High before DMAGx High
t_DGWR
DMAGx High to WR, RD, DMAGx Low
9 + DT/4
15 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
6 – DT/8
17 + DT
–0.5
8 + 9DT/16
0
7
0
2
10 + 5DT/8 + W
1 + DT/16
3 + DT/16
0
2
11 + 9DT/16 + W
0
3
5 + 3DT/8 + HI
9 + DT/4
15 + DT/4
ns
6 + 3DT/8
ns
12 + 5DT/8
ns
–2 – DT/8
6 – DT/8
ns
17 + DT
ns
–1.0
ns
8 + 9DT/16
ns
0
7
ns
0
2
ns
10 + 5DT/8 + W
ns
1 + DT/16
3 + DT/16
ns
0
2
ns
11 + 9DT/16 + W
ns
0
3
ns
5 + 3DT/8 + HI
ns
W = (number of wait states specified in WAIT register) × t_CK.
HI = t_CK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1_{Only required for recognition in the current cycle.}
2_{tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the}
data can be driven t_DATDRH after DMARx is brought high.
3_{tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9DT/16 + (n × tCK) where}
n equals the number of extra cycles that the access is prolonged.
4_{See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.}
–32–
REV. B