ADSP-2106X Datasheet, PDF (25/47 Pages) Analog Devices – DSP Microcomputer Family

ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
Parameter
Timing Requirements:
t_SADRI
t_HADRI
t_SRWLI
t_HRWLI
t_HRWLI
Address, SW Setup before CLKIN
Address, SW Hold before CLKIN
RD/WR Low Setup before CLKIN¹
RD/WR Low Hold after CLKIN
RD/WR Low Hold after CLKIN
44 MHz/50 MHz²
t_RWHPI
t_SDATWH
t_HDATWH
RD/WR Pulse High
Data Setup before WR High
Data Hold after WR High
ADSP-21061 (5 V)
Min
Max
14 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
–3.5 – 5DT/16
3
3
1
5 + DT/2
8 + 7DT/16
8 + 7DT/16
ADSP-21061L (3.3 V)
Min
Max
Unit
14 + DT/2
ns
5 + DT/2
ns
8.5 + 5DT/16
ns
–4 – 5DT/16
8 + 7DT/16
ns
–3.5 – 5DT/16 8 + 7DT/16
ns
3
ns
3
ns
1
ns
Switching Characteristics:
t_SDDATO
t_DATTR
t_DACKAD
t_ACKTR
Data Delay after CLKIN
Data Disable after CLKIN³
ACK Delay after Address, SW⁴
ACK Disable after CLKIN⁴
0 – DT/8
–1 – DT/8
19 + 5DT/16
7 – DT/8
8
6 – DT/8
0 – DT/8
–1 – DT/8
19 + 5DT/16 ns
7 – DT/8
ns
8
ns
6 – DT/8
ns
NOTES
1_{tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)}
= 4 + DT/8.
2_{This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), o perating at tCK <25 ns. For all other devices,}
use the preceding timing specification of the same name.
3_{See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.}
4_{tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have}
setup times greater than 19 + 3DT/4, then ACK is valid 15.5 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t _ACKTR.
CLKIN
ADDRESS
SW
ACK
t _SADRI
t _DACKAD
t _HADRI
t _ACKTR
READ ACCESS
RD
DATA
(OUT)
WRITE ACCESS
WR
DATA
(IN)
t _SDDATO
t _SRWLI
t _HRWLI
t _RWHPI
t _DATTR
t _SRWLI
t _SDATWH
t _HRWLI
t _HDATWH
t _RWHPI
REV. B
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