ADAU1977 Datasheet, PDF (32/64 Pages) Analog Devices – Quad ADC with Diagnostics

ADAU1977
SPI MODE
By default, the ADAU1977 is in I²C mode. To invoke SPI control
mode, pull CLATCH low three times. This can be done by per-
forming three dummy writes to the SPI port (the ADAU1977 does
not acknowledge these three writes; see Figure 41). Beginning
with the fourth SPI write, data can be written to or read from
the device. The ADAU1977 can be taken out of SPI mode only
by a full reset initiated by power cycling the device.
The SPI port uses a 4-wire interface, consisting of the CLATCH,
CCLK, CIN, and COUT signals, and it is always a slave port.
The CLATCH signal should go low at the beginning of a trans-
action and high at the end of a transaction. The CCLK signal
latches CIN on a low-to-high transition. COUT data is shifted out
of the ADAU1977 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CIN signal carries the serial input
data, and the COUT signal carries the serial output data. The
COUT signal remains tristated until a read operation is requested.
This allows direct connection to other SPI-compatible peripheral
COUT ports for sharing the same system controller port. All
SPI transactions have the same basic format shown in Table 24.
A timing diagram is shown in Figure 3. All data should be written
MSB first.
Chip Address R/W
The LSB of the first byte of an SPI transaction is a R/W bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in Table 22.
Table 22. ADAU1977 SPI Address and R/W Byte Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
0
0
R/W
Register Address
The 8-bit address word is decoded to a location in one of the
registers. This address is the location of the appropriate register.
Data Sheet
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial register address is
written followed by a continuous sequence of data for consecutive
register locations.
A sample timing diagram for a single-word SPI write operation to a
register is shown in Figure 42. A sample timing diagram of a single-
word SPI read operation is shown in Figure 43. The COUT pin
goes from being high-Z to being driven at the beginning of Byte 3.
In this example, Byte 0 to Byte 1 contain the device address, the
R/W bit, and the register address to be read. Subsequent bytes
carry the data from the device.
Standalone Mode
The ADAU1977 can also be operated in standalone mode.
However, in standalone mode, the boost converter, microphone
bias, and diagnostics blocks are powered down. To set the part
in standalone mode, pull the SA_MODE pin to IOVDD. In this
mode, some pins change functionality to provide more flexibility
(see Table 23 for more information).
Table 23. Pin Functionality in Standalone Mode
Pin Function Setting
Description
ADDR0
0
I²S SAI format
1
TDM modes, determined by the
SDATAOUT2 pin
ADDR1
0
Master mode SAI
1
Slave mode SAI
SDA
0
MCLK = 256 × fS, PLL on
1
MCLK = 384 × fS, PLL on
SCL
0
48 kHz sample rate
1
96 kHz sample rate
SDATAOUT2 0
TDM4—LRCLK pulse
1
TDM8—LRCLK pulse
FAULT
0
Slot 1 to Slot 4 in TDM8
1
Slot 5 to Slot 8 in TDM8
If set for TDM8 mode, the FAULT pin is used as an input for
assigning the ADC data slot to prevent collision with other data
on TDM bus.
Table 24. Generic Control Word Format
Byte 0
Byte 1
Device Address[6:0], R/W
Register Address[7:0]
1 _{Continues to end of data.}
Byte 2
Data[7:0]
Byte 3¹
Data[7:0]
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