ADAU1977 Datasheet, PDF (1/64 Pages) Analog Devices – Quad ADC with Diagnostics

Data Sheet
Quad ADC with Diagnostics
ADAU1977
FEATURES
Programmable microphone bias (5 V to 9 V) with diagnostics
Four 10 V rms capable direct-coupled differential inputs
On-chip PLL for master clock
Low EMI design
106 dB ADC dynamic range
−95 dB THD + N
Selectable digital high-pass filter
24-bit ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I²C/SPI control
Software-controllable clickless mute
Software power-down
Right justified, left justified, I²S justified, and TDM modes
Master and slave operation modes
40-lead LFCSP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Active noise cancellation system
GENERAL DESCRIPTION
The ADAU1977 incorporates four high performance analog-to-
digital converters (ADCs) with direct-coupled inputs capable of
10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecture
with continuous time front end for low EMI. The ADCs can be
connected to the electret microphone (ECM) directly and pro-
vide the bias for powering the microphone. Built-in diagnostic
circuitry detects faults on input lines and includes comprehensive
diagnostics for faults on microphone inputs. The faults reported
are short to battery, short to microphone bias, short to ground,
short between positive and negative input pins, and open input
terminals. In addition, each diagnostic fault is available as an
IRQ flag for ease in system design. An I²C/SPI control port is
also included. The ADAU1977 uses only a single 3.3 V supply.
The part internally generates the microphone bias voltage. The
microphone bias is programmable in a few steps from 5 V to 9 V.
The low power architecture reduces the power consumption.
An on-chip PLL can derive the master clock from an external
clock input or frame clock (sample rate clock). When fed with
a frame clock, the PLL eliminates the need for a separate high
frequency master clock in the system. The ADAU1977 is
available in a 40-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
MICBIAS
MB_GND
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
5V TO 9V
PROG
BIAS
BOOST
CONVERTER
I_OUT 50mA
PGND
ADC
ADC
ADC
ADC
VBAT
AGND1 AGND3
AVDDx
AVDD2
DIAGNOSTICS
BG
REF
PLL
AGND2
AGNDx
AGND2
ADAU1977
3.3V TO 1.8V
REGULATOR
DVDD
I2C/SPI
CONTROL
IOVDD
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CL ATCH
FAULT
PD/RST
Figure 1.
Rev. A
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