AD9868 Datasheet, PDF (32/36 Pages) Analog Devices – Broadband Modem Mixed-Signal Front End

AD9868
Because the CPGA processes signals in the continuous time
domain, its performance vs. bias setting remains mostly
independent of the sample rate. Table 25 shows how the typical
current consumption seen at AVDD varies as a function of
Register 0x13, Bits [7:5], while the remaining bits are maintained at
their default settings of 0. Only four of the possible settings result
in any reduction in current consumption relative to the default
setting. Reducing the bias level typically results in degradation
in the THD vs. frequency performance as shown in Figure 35.
This is due to a reduction of the amplifier’s unity gain bandwidth,
while the SNR performance remains relatively unaffected.
Table 25. Analog Supply Current vs. CPGA Bias Settings at
fADC = 65 MSPS
Bit 7
Bit 6
Bit 5
∆mA
0
0
0
0
0
0
1
−27
0
1
0
−42
0
1
1
−51
1
0
0
−55
1
0
1
+27
1
1
0
+69
1
1
1
+27
65.0
–20
SNR_RxPGA = 0dB
62.5
–25
60.0
–30
57.5
–35
55.0
SNR_RxPGA = 36dB
–40
52.5
–45
50.0
–50
THD_RxPGA = 0dB
47.5
–55
45.0
–60
42.5
40.0
000
THD_RxPGA = 36dB
001
010
011
CPGA BIAS SETTING-BITS (7:5)
–65
–70
100
Figure 35. THD vs. fIN Performance and CPGA Bias Settings (000, 001, 010, 100
with RxPGA = 0 and +36 dB, AIN = −1 dBFS, LPF set to 26 MHz, fADC = 50 MSPS)
The SPGA is implemented as a switched capacitor amplifier,
therefore, its performance vs. bias level is mostly dependent on
the sample rate. Figure 36 shows how the typical current consump-
tion seen at AVDD varies as a function of Register 0x13, Bits [4:3]
and sample rate, while the remaining bits are maintained at the
default setting of 0. Figure 37 shows how the SNR and THD
performance is affected for a 10 MHz sine wave input as the
ADC sample rate is swept from 20 MHz to 80 MHz. The SNR
and THD performance remains relatively stable, suggesting that
the SPGA bias can often be reduced from its default setting
without impacting the device’s overall performance.
210
205
200
01
195
00
190
185
10
180
11
175
170
20
30
40
50
60
70
80
ADC SAMPLE RATE (MSPS)
Figure 36. AVDD Current vs. SPGA Bias Setting and Sample Rate
61
–54
60
–56
59
–58
58
SNR-00 _–60
SNR-01
57
SNR-10 _–62
SNR-11
56
–64
55
–66
54
THD-00
–68
THD-01
53
THD-10
–70
THD-11
52
–72
51
–74
20
30
40
50
60
70
80
SAMPLE RATE (MSPS)
Figure 37. SNR and THD Performance vs. fADC and SPGA Bias Setting with
RxPGA = 0 dB, fIN = 10 MHz, LPF set to 26 MHz, AIN = −1 dBFS
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