AD9868 Datasheet, PDF (15/36 Pages) Analog Devices – Broadband Modem Mixed-Signal Front End

Figure 5 illustrates the timing requirements for a write opera-
tion to the SPI port. After the serial port enable (SEN) signal
goes low, data (SDIO) pertaining to the instruction header is
read on the rising edges of the clock (SCLK). To initiate a write
operation, the read/not-write bit is set low. After the instruction
header is read, the eight data bits pertaining to the specified
register are shifted into the SDIO pin on the rising edge of the
next eight clock cycles. If a multibyte communication cycle is
specified, the destination address is decremented (MSB first)
and shifts in another eight bits of data. This process repeats until
all the bytes specified in the instruction header (N1 bit, N0 bit)
are shifted into the SDIO pin. SEN must remain low during the
data transfer operation, only going high after the last bit is
shifted into the SDIO pin.
AD9868
Figure 6 illustrates the timing for a 3-wire read operation to the
SPI port. After SEN goes low, data (SDIO) pertaining to the
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high.
After the address bits of the instruction header are read, the
eight data bits pertaining to the specified register are shifted out
of the SDIO pin on the falling edges of the next eight clock
cycles. If a multibyte communication cycle is specified in the
instruction header, a similar process as previously described for
a multibyte SPI write operation applies. The SDO pin remains
three-stated in a 3-wire read operation.
Figure 7 illustrates the timing for a 4-wire read operation to the
SPI port. The timing is similar to the 3-wire read operation with
the exception of the data appearing at the SDO pin, while the
SDIO pin remains at high impedance throughout the operation.
The SDO pin is an active output only during the data transfer
phase and remains three-stated at all other times.
SEN
SCLK
SDIO
t_S 1/f_SCLK
t_H
t_HI
t_LOW
t_DS
t_DH
R/W N1
N0
A0
D7 D6 D1 D0
Figure 5. SPI Write Operation Timing
SEN
SCLK
SDIO
t_S 1/f_SCLK
t_HI
t_LOW
t_DS
t_DH
t_DV
t_EZ
R/W N1 A2 ^A1 A0
D7 D6 D1 D0
Figure 6. SPI 3-Wire Read Operation Timing
SEN
SCLK
SDIO
SDO
t_S 1/f_SCLK
t_HI
t_LOW
t_DS
t_DH
t_EZ
R/W N1 A2 ^A1 A0
t_DV
t_EZ
D7 D6 D1 D0
Figure 7. SPI 4-Wire Read Operation Timing
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