AD9857_15 Datasheet, PDF(31/40 Page) Analog Devices – CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

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AD9857_15 Datasheet, PDF (31/40 Pages) Analog Devices – CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

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SYSCLK/N

SYSCLK/2N

SYSCLK/4N

PDCLK

TxENABLE

D<13:0>

SIGNAL PATH I

SIGNAL PATH Q

INVCIC CLOCK

DON'T CARE

LATENCY THROUGH DATA ASSEMBLER LOGIC IS

3 PDCLK CYCLES

INVERSE CIC

FILTER SETUP

TIME

Figure 33. Latency from D<13:0> to Signal Processing Chain, Four PDCLK Cycles

AD9857

SYSCLK/N

SYSCLK/2N

SYSCLK/4N

PDCLK

TxENABLE

D<13:0> DON'T CARE

SIGNAL PATH I

SIGNAL PATH Q

INVCIC CLOCK

LATENCY THROUGH DATA ASSEMBLER LOGIC INVERSE CIC FILTER SETUP TIME

IS 3 PDCLK CYCLES

Figure 34. Latency from D<13:0> to Signal Processing Chain, Five PDCLK Cycles

Rev. C| Page 31 of 40

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