AD9857_15 Datasheet, PDF (1/40 Pages) Analog Devices – CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

CMOS 200 MSPS 14-Bit
Quadrature Digital Upconverter
AD9857
FEATURES
200 MHz internal clock rate
14-bit data path
Excellent dynamic performance:
80 dB SFDR @ 65 MHz (±100 kHz) AOUT
4× to 20× programmable reference clock multiplier
Reference clock multiplier PLL lock detect indicator
Internal 32-bit quadrature DDS
FSK capability
8-bit output amplitude control
Single-pin power-down function
Four programmable, pin-selectable signal profiles
SIN(x)/x correction (inverse SINC function)
Simplified control interface
10 MHz serial, 2-wire or 3-wire SPI®-compatible
3.3 V single supply
Single-ended or differential input reference clock
80-lead LQFP surface-mount packaging
Three modes of operation:
Quadrature modulator mode
Single-tone mode
Interpolating DAC mode
APPLICATIONS
HFC data, telephony, and video modems
Wireless base station
Agile, LO frequency synthesis
Broadband communications
PARALLEL
DATA IN
(14-BIT)
INVERSE
CIC FILTER
I
14
INV
14
CIC
Q
FUNCTIONAL BLOCK DIAGRAM
FIXED
INTER-
POLATOR ^PROGRAMMABLE
INTERPOLATOR
(4 )
CIC
(2 - 63 )
QUADRATURE
MODULATOR
INVERSE
SINC
FILTER
DDS
CORE
CONTROL REGISTERS
TUNING
WORD ³²
TIMING AND CONTROL
AD9857
14
8
14-BIT
DAC
OUTPUT
SCALE
VALUE
DAC_RSET
IOUT
IOUT
POWER- PROFILE
DOWN SELECT
LOGIC LOGIC
CLOCK
MULTIPLIER
(4 – 20 )
MODE
CONTROL
REFCLK
REFCLK
PDCLK/ TxENABLE RESET CIC
SERIAL
FUD
OVERFLOW PORT
DIGITAL PS1 PS0
POWER-
DOWN
Figure 1.
PLL
LOCK
CLOCK
INPUT
MODE
Rev. C
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