ADSP-BF538_07 Datasheet, PDF (30/56 Pages) Analog Devices – Blackfin® Embedded Processor

ADSP-BF538/ADSP-BF538F
Asynchronous Memory Write Cycle Timing
Table 20 and Table 21 on Page 31 and Figure 13 and Figure 14
on Page 31 describe asynchronous memory write cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 20. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
t_SARDY
ARDY Setup Before the Falling Edge of CLKOUT
t_HARDY
ARDY Hold After the Falling Edge of CLKOUT
Switching Characteristics
t_DDAT
t_ENDAT
t_DO
t_HO
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT¹
Output Hold After CLKOUT¹
1 _{Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.}
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
CLKOUT
t _DO
t_HO
AMSx
Min
Max
Unit
4.0
ns
0.0
ns
6.0
ns
1.0
ns
6.0
ns
0.8
ns
ABE1–0
ADDR19–1
AWE
ARDY
DATA15–0
BE, ADDRESS
t_DO
t_HO
t _SARDY
t _ENDAT
t _SARDY
WRITE DATA
t_HARDY
t _HARDY
t _DDAT
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. 0 | Page 30 of 56 | May 2007