ADSP-BF538_07 Datasheet, PDF (1/56 Pages) Analog Devices – Blackfin® Embedded Processor

FEATURES
Up to 533 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of program-
ming and compiler friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.25 V core V_DD with on-chip voltage regulation
2.5 V to 3.3 V I/O V_DD
Up to 3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K Ï« 16-bit or 256K Ï« 16-bit of flash memory
(ADSP-BF538F only)
Memory management unit providing memory protection
Blackfin^®
Embedded Processor
ADSP-BF538/ADSP-BF538F
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI^® and external
memory
PERIPHERALS
Parallel peripheral interface (PPI) supporting ITU-R 656 video
data formats
Four dual-channel, full-duplex synchronous serial ports,
supporting 16 stereo I²S^® channels
Two DMA controllers supporting 26 peripheral DMAs
Four memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
Three SPI-compatible ports
Three 32-bit timer/counters with PWM support
Three UARTs with support for IrDA^®
Two TWI controllers compatible with I²C^® industry standard
Up to 54 general-purpose I/O pins (GPIO)
Real time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of 0.5Ï« to 64Ï« frequency multiplication
Debug/JTAG interface
G P IO
PORT
C
G P IO
PORT
D
G P IO
PORT
E
TWI0-1
C A N 2.0B
G PIO
S P I1- 2
U A R T1 -2
SPORT2-3
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
B
INTERRUPT
CONTROLLER
DMA
C O N TR OL LE R1
L1
IN ST R U C TIO N
M EM O R Y
L1
DATA
M EM O RY
DMA
C ON T R OL LER 0
DMA CORE
BUS 1
DMA
EXTERNAL
BUS 1
DMA CORE BUS 0
DMA
EXTERNAL
BUS 0
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
512kB OR 1MB
FLASH MEMORY
(ADSP-BF538F O NLY)
BOOT ROM
WATCHDOG
TIM E R
RTC
PPI
TIM ER 0-2
SPI0
UART0
SP O R T 0 -1
G PIO
PORT
F
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. 0
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