AD9980_15 Datasheet, PDF (30/44 Pages) Analog Devices – High Performance 8-Bit Display Interface

AD9980
Preliminary Technical Data
0x12 7
Hsync Source Override
This is the active Hsync override. Setting this to 0
allows the chip to determine the active Hsync source.
Setting it to 1 uses Bit 6 of Register 0x12 to determine
the active Hsync source. Power-up default value is 0.
Table 16. Active Hsync Source Override
Override
Result
0
Hsync Source determined by chip
1
Hsync Source determined by user
Register 0x12, Bit 6
0x12 6
Hsync Source
This bit selects the source of the Hsync for PLL and
sync processing only if Bit 7 of Register 0x12 is set to 1
or if both syncs are active. Setting this bit to 0 specifies
the Hsync from the input pin. Setting it to 1 selects
Hsync from SOG. Power-up default is 0.
Table 17. Active Hsync Select Settings
Select
Result
0
Hsync Input
1
Hsync from SOG
0x12 5
Hsync Input Polarity Override
This bit sets whether the chip selects the Hsync input
polarity or if it is specified. Setting this bit to 0 allows
the chip to automatically select the polarity of the
input Hsync. Setting this bit to 1 indicates that Bit 4 of
Register 0x12 specifies the polarity. Power-up default
is 0.
Table 18. Hsync Input Polarity Override Settings
Override Bit
Result
0
Hsync Polarity Determined by Chip
1
Hsync Polarity Determined by User
Register 0x12, Bit 4
0x12 4
Input Hsync Polarity
If Bit 5 of Register 0x12 is 1, the value of this bit
specifies the polarity of the input Hsync. Setting this
bit to 0 indicates an active low Hsync; setting this bit
to 1 indicates an active high Hsync. Power-up default
is 1.
Table 19. Hsync Input Polarity Settings
Hsync Polarity Bit Result
0
Hsync Input Polarity is Negative
1
Hsync Input Polarity is Positive
0x12 3
Hsync Output Polarity
This bit sets the polarity of the Hsync output. Setting
this bit to 0 sets the Hsync output to active low. Setting
this bit to 1 sets the Hsync output to active high.
Power-up default setting is 1.
Table 20. Hsync Output Polarity Settings
Hsync Output
Polarity Bit
Result
0
Hsync Output Polarity is Negative
1
Hsync Output Polarity is Positive
0x13 7:0 Hsync Duration
An 8-bit register that sets the duration of the Hsync
output pulse. The leading edge of the Hsync output is
triggered by the internally-generated, phase-adjusted
PLL feedback clock. The AD9980 then counts a
number of pixel clocks equal to the value in this
register. This triggers the trailing edge of the Hsync
output, which is also phase-adjusted.
VSYNC CONTROLS
0x14 7
Vsync Source Override
This is the active Vsync override. Setting this to 0
allows the chip to determine the active Vsync source.
Setting it to 1 uses Bit 6 of Register 0x14 to determine
the active Vsync source. Power-up default value is 0.
Table 21. Active Vsync Source Override
Override
Result
0
Vsync source determined by chip
1
Vsync source determined by user
Register 0x14, Bit 6
0x14 6
Vsync Source
This bit selects the source of Vsync for sync
processing only if Bit 7 of Register 0x14 is set to 1.
Setting Bit 6 to 0 specifies Vsync from the input pin.
Setting it to 1 selects Vsync from the sync separator.
Power-up default is 0.
Table 22. Active Vsync Select Settings
Select
Result
0
Vsync input
1
Vsync from sync separator
0x14 5
Vsync Input Polarity Override
This bit sets whether the chip selects the Vsync input
polarity or if it is specified. Setting this bit to 0 allows
the chip to automatically select the polarity of the
input Vsync. Setting this bit to 1 indicates that Bit 4 of
Register 0x14 specifies the polarity. Power-up default
is 0.
Table 23. Vsync Input Polarity Override Settings
Override Bit Result
0
Vsync polarity determined by chip
1
Vsync polarity determined by user
Register 0x14, Bit 4
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