AD9980_15 Datasheet, PDF (29/44 Pages) Analog Devices – High Performance 8-Bit Display Interface

AD9980
PHASE ADJUST
0x04 7:3
Phase adjustment for the DLL to generate the ADC
clock. A 5-bit value that adjusts the sampling phase in
32 steps across one pixel time. Each step represents an
11.25° shift in sampling phase. The power up default
is 16.
INPUT GAIN
0x05 6:0 Red Channel Gain Adjust
The 7-Bit Red Channel Gain Control. The AD9980
can accommodate input signals with a full-scale range
of 0.5 V to 1.0 V p-p. Setting the red gain to 127
corresponds to an input range of 1.0 V. A red gain of 0
establishes an input range of 0.5 V. Note that
increasing red gain results in the picture having less
contrast (the input signal uses fewer of the available
converter codes). Values written to this register will
not be updated until the following register
(Register 0x06) has been written to 0x00. The power-
up default is 100 0000.
0x07 6:0 Green Channel Gain Adjust
The 7-Bit Green Channel Gain Control. See red
channel gain adjust above. Register update requires
writing 0x00 to Register 0x08.
0x09 6:0 Blue Channel Gain Adjust
The 7-Bit Blue Channel Gain Control. See red channel
gain adjust above. Register update requires writing
0x00 to Register 0x0A.
INPUT OFFSET
0x0B 7:0 Red Channel Offset
The 8-Bit MSB of the Red Channel Offset Control.
Along with the LSB in the following register, there are
nine bits of dc offset control in the red channel. The
offset control shifts the analog input, resulting in a
change in brightness. Note that the function of the
offset register depends on whether auto-offset is
enabled (Register 0x1B, Bit 5).
If auto-offset is disabled, the lower seven bits of the
offset registers (for the red channel Register 0x0B, Bits
[5:0] plus Register 0x0C, Bit 7) control the absolute
offset added to the channel. The offset control
provides a ±63 LSBs of adjustment range, with one
LSB of offset corresponding to 1 LSB of output code.
If auto-offset is enabled, the 9-bit offset (comprised of
the 8 bits of the MSB register and Bit 7 of the
following register) determines the clamp target code.
The 9-bit offset consists of one sign bit plus eight bits.
If the register is programmed to 130, then the output
code will be equal to 130 at the end of the clamp
period. Incrementing the offset register setting by
1 LSB will add 1 LSB of offset, regardless of the auto-
offset setting. Values written to this register are not
updated until the LSB register (Register 0x0C) has also
been written.
0x0C 7
Red Channel Offset LSB
The LSB of the red channel offset control which
combines with the eight bits of MSB in the previous
register to make nine bits of offset control.
0x0D 7:0 Green Channel Offset
The 8-Bit Green Channel Offset Control. See red
channel offset (0x0B). Update of this register occurs
only when Register 0x0E is also written.
0x0E 7
Green Channel Offset LSB
The LSB of the green channel offset control which
combines with the eight bits of MSB in the previous
register to make nine bits of offset control.
0x0F 7:0 Blue Channel Offset
The 8-Bit Blue Channel Offset Control. See red
channel offset (0x0B). Update of this register occurs
only when Register 0x10 is also written.
0x10 7
Blue Channel Offset LSB
The LSB of the blue channel offset control which
combines with the eight bits of MSB in the previous
register to make nine bits of offset control.
HSYNC CONTROLS
0x11 7:0 Sync Separator Threshold
This register sets the threshold of the sync separator’s
digital comparator. The value written to this register is
multiplied by 200 ns to get the threshold value.
Therefore, if a value of 5 is written, the digital
comparator threshold is 1 µs and any pulses less than
1 µS are rejected by the sync separator. There is some
variability to the 200 ns multiplier value. The maxi-
mum variability over all operating conditions is ±20%
(160 nS to 240 ns). Since normal Vsync and Hsync
pulse widths differ by a factor of about 500 or more,
the 20% variability is not an issue. The power-up
default value is 32 DDR.
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