AD9848_15 Datasheet, PDF (30/32 Pages) Analog Devices – CCD Signal Processors with Integrated Timing Driver

AD9848/AD9849
AD9848/AD9849
CCDIN
29
13 14
H1 H2
17 18
H3 H4
20
RG
SIGNAL
OUT
Internal Mode Circuit Configuration
The AD9848/AD9849 may be used in Internal Mode using the
circuit configuration of Figure 24. Internal Mode uses the same
circuit as Figure 21, except that the horizontal pulses (CLPOB,
CLPDM, PBLK, and HBLK) are internally generated in the
AD9848/AD9849. These pins may be grounded when Internal
Mode is used. Only the HD and VD signals are required from
the ASIC.
2
HD/VD
INPUTS
H1 H2
RG
CCD IMAGER
H2 H1
Figure 22b. CCD Connections (4 H-Clock)
44 43
42 41 40 39
AD9848/AD9849
Figure 24. Internal Mode Circuit Configuration
AD9848/AD9849
23
CLI
ASIC
TIMING EXAMPLES FOR DIFFERENT SEQUENCES
2
SEQUENCE 2
V
MASTER CLOCK
Figure 23a. CLI Connection, DC-Coupled
4
AD9848/AD9849
28
23
CLI
LPF
1nF
ASIC
MASTER CLOCK
Figure 23b. CLI Connection, AC-Coupled
SEQUENCE 3
10
SEQUENCE 2
H
48
Figure 25. Typical CCD
–30–
REV. A