AD9848_15 Datasheet, PDF (29/32 Pages) Analog Devices – CCD Signal Processors with Integrated Timing Driver

AD9848/AD9849
3V
DIGITAL
SUPPLY
0.1␮F
6
CLOCK
INPUTS
SERIAL
3 _INTERFACE
3V
DRIVER
SUPPLY
0.1␮F
DATA ¹²
OUTPUTS
D2 ₁
D3 ₂
D4 ₃
D5 ₄
D6
5
DVSS3 ₆
DVDD3 ₇
D7 ₈
D8 ₉
D9 ₁₀
D10 ₁₁
(MSB) D11 ₁₂
48 47 46 45 44 43 42 41 40 39 38 37
PIN 1
IDENTIFIER
AD9849
TOP VIEW
(Not to Scale)
SL
36
REFT
35
REFB
34
CMLEVEL
33
AVSS3
32
AVDD3
31
BYP3
30
CCDIN
29
BYP2
28
BYP1
27
AVDD2
26
AVSS2
25
1␮F
1␮F
0.1␮F
13 14 15 16 17 18 19 20 21 22 23 24
0.1␮F 0.1␮F 0.1␮F
H DRIVER
SUPPLY
RG DRIVER
SUPPLY
0.1␮F
3V
ANALOG
SUPPLY
CLOCK
INPUT
0.1␮F
3V
ANALOG
SUPPLY
0.1␮F
CCD
SIGNAL
3V
ANALOG
SUPPLY
0.1␮F
0.1␮F
0.1␮F
5
HIGH SPEED
CLOCKS
Figure 21. Recommend Circuit Configuration for External Mode
Driving the CLI Input
The AD9848/AD9849’s master clock input (CLI) may be used in
two different configurations, depending on the application.
Figure 23a shows a typical dc-coupled input from the master clock
source. When the dc-coupled technique is used, the master clock
signal should be at standard 3 V CMOS logic levels. As shown in
Figure 23b, a 1000 pF ac-coupling capacitor may be used between
the clock source and the CLI input. In this configuration, the
CLI input will self-bias to the proper dc voltage level of approxi-
mately 1.4 V. When the ac-coupled technique is used, the
master clock signal can be as low as ± 500 mV in amplitude.
AD9848/AD9849
CCDIN
29
17 18
H3 H4
13 14
H1 H2
20
RG
SIGNAL
OUT
H1 H2
RG
CCD IMAGER
Figure 22a. CCD Connections (2 H-Clock)
REV. A
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