AD9628_15 Datasheet, PDF (30/42 Pages) Analog Devices – 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

AD9628
Data Sheet
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)² + 10 ] ^{(SNRLF /10)}
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 58.
80
75
0.05ps
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (26, in the case of the
AD9628).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
70
0.2ps
65
60
0.5ps
55
1.0ps
50
1.5ps
2.0ps
45
3.0ps 2.5ps
1
10
100
1k
FREQUENCY (MHz)
Figure 58. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9628.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
See the AN-501 Application Note and the AN-756 Application
Note for more information.
CHANNEL/CHIP SYNCHRONIZATION
The AD9628 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized
to the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 59, the analog core power dissipated by
the AD9628 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 59 was
taken in CMOS mode using the same operating conditions as those
used for the power supplies and power consumption specifications
in Table 1 with a 5 pF load on each output driver.
100
240
90
80
I_AVDD
70
190
60
50
140
TOTAL POWER
40
30
90
20
I_DRVDD
10
0
40
5
25
45
65
85
105
125
ENCODE RATE (MSPS)
Figure 59. AD9628-125 Power and Current vs. Clock Rate (1.8 V CMOS
Output Mode)
90
200
80
I_AVDD
180
70
160
60
140
50
TOTAL POWER
120
40
100
30
20
80
10
I_DRVDD
60
0
40
5
25
45
65
85
105
ENCODE RATE (MSPS)
Figure 60. AD9628-105 Power and Current vs. Clock Rate (1.8 V CMOS
Output Mode)
Rev. C | Page 30 of 42