AD9628_15 Datasheet, PDF (15/42 Pages) Analog Devices – 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

Data Sheet
AD9628
CLK+ 1
CLK– 2
SYNC 3
NC 4
NC 5
NC 6
NC 7
NC 8
NC 9
DRVDD 10
NC 11
NC 12
D0– (LSB) 13
D0+ (LSB) 14
D1– 15
D1+ 16
PIN 1
INDICATOR
AD9628
INTERLEAVED PARALLEL LVDS
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 OR+
42 OR–
41 D11+ (MSB)
40 D11– (MSB)
39 D10+
38 D10–
37 DRVDD
36 D9+
35 D9–
34 D8+
33 D8–
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37 DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, AVDD
59, 60, 63, 64
Supply
Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7, 8, 9, NC
11, 12
No Connect. Do not connect to these pins.
0
AGND, Exposed Ground
The exposed thermal pad on the bottom of the package provides the analog ground
Pad
for the part. This exposed pad must be connected to ground for proper operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
55
VREF
Input/Output Voltage Reference Input/Output.
56
SENSE
Input
Reference Mode Selection.
58
RBIAS
Input/Output External Reference Bias Resistor. Connect to 10 kΩ (1% tolerance) resistor to ground.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Rev. C | Page 15 of 42