SSM2163_15 Datasheet, PDF (3/16 Pages) Analog Devices – Digitally Controlled 8 3 2 Audio Mixer

SSM2163
Timing
Symbol Description
Timing Description
Min Typ Max Units
t_CL
Input Clock Pulse Width
50
ns
t_CH
Input Clock Pulse Width
50
ns
t_DS
Data Setup Time
25
ns
t_DH
Data Hold Time
35
ns
t_CW
Positive CLK Edge to End of Write 25
ns
t_WC
Write to Clock Setup Time
35
ns
t_LW
End of Load Pulse to Next Write
20
ns
t_WL
End of Write to Start of Load
20
ns
OBSOLETE ^tL
Load Pulse Width
250
ns
t_W3
Load Pulse Width (3-Wire Mode)
250
ns
t_PD
Propagation Delay from Rising
10 80 160 ns
Clock to SDO Transition
(R_L = 220 kΩ, C_L = 20 pF)
NOTES
1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the positive
edge.
2. For SPI or microwire three-wire bus operation, tie LD to WRITE and use WRITE pulse to drive
both pins. (This generates an automatic internal LD signal.)
3. If an idle HI clock is used, t_CW and t_WL are measured from the final negative transition to the idle
state.
4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain levels. Re-
fer to the Address/Data Decoding Truth Table.
5. Data must be sent MSB first.
1
CLK
0
1
DATA
0
1
WRITE & LOAD
0
D7
D6
D5
D4
D3
D2
D1
D0
1
CLK
0
1
DATA
0
1
WRITE & LOAD
0
1
SDO
0
t_CL
t_CH
t_DS
t_DH
t_WC
t_PD
t_CW
t_W3
Figure 1. Three-Wire Mode Timing Diagram
REV. 0
–3–