SSM2163_15 Datasheet, PDF (14/16 Pages) Analog Devices – Digitally Controlled 8 3 2 Audio Mixer

SSM2163
14
V_OUTL
+V +5V
1/2
OP279
16Ω
220µF
+
50k
SSM2163
15
V_OUTR
1/2
OP279
16Ω
220µF
+
50k
LEFT
HEADPHONE
RIGHT
HEADPHONE
(P3.0) RxD
DATA IN
(P3.1) TxD
CLK
80C51 µC
P1.4
P1.2
P1.3
+5V
10k
WRITE
LD
SSM2163
SYSMUTE
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 28. A Single-Supply Stereo Headphone Driver
Figure 30. Interfacing the 80C51 µC to an SSM2163 in
4-Wire Mode
OBSOLETE The op amp’s input offset voltage is only 4 mV maximum, so
the SSM2163 output can be dc coupled. The headphone output
is ac coupled through a 220 µF capacitor. The large coupling
capacitor is required because of the low impedance of the
headphones, which can range from 32 Ω to 600 Ω. An additional
16 Ω resistor is used in series with the output capacitor to protect
the op amp’s output stage by limiting capacitor discharge current.
Microcomputer Interfaces
The SSM2163 serial data input provides an easy interface to a
variety of single chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for
communicating with the SSM2163. In cases where no serial
port is provided, or it is being used for some other purpose
(such as an RS-232 communications interface), the SSM2163
can easily be addressed in software.
The SSM2163 can operate in either a 3-wire or 4-wire mode.
In most cases, the 3-wire mode is more practical, due to
An 80C51 ␮C Interface
A typical interface between the SSM2163 and an 80C51 µC is
shown in Figure 30. This interface uses the 80C51’s internal
serial port. The serial port is programmed for Mode 0 operation,
which functions as a simple 8-bit shift register. The 80C51’s Port
3.0 pin functions as the serial data output, while Port 3.1 serves
as the serial clock.
When data is written to the serial buffer register (SBUF, at
Special Function Register location 99H), the data is
automatically converted to serial format and clocked out via
Port 3.0 and Port 3.1. After 8 bits have been transmitted, the
Transmit Interrupt flag (SCON.1) is set and the next 8 bits
can be transmitted.
The 80C51 transmits serial data in Least Significant Bit (LSB)-
first format. The SSM2163, on the other hand, requires data in
MSB format. A BYTESWAP routine swaps the order of the bits
reduced PC board traces and compatibility with µC serial
before transmission.
interface protocols. A typical interface, using the 80C51 µC, is
The SSM2163 requires the Chip Select to go low at the begin-
shown in Figure 29, while the interface waveforms are shown in ning of the serial data transfer. After each 8 bits (either address
the Timing Diagram, 3-Wire Mode, Figure 1.
or attenuation value) are transmitted, Chip Select must go high
to latch data into the appropriate register. Chip Select is controlled
(P3.0) RxD
(P3.1) TxD
DATA IN
CLK
by the 80C51’s port 1.4 pin.
Software for the 80C51 Interface
A software routine for the SSM2163 to 80C51 interface is
P1.4
WRITE
shown in Listing 1. The routine transfers the 6-bit attenuation
80C51 µC
LD
+5V
SSM2163
10k
P1.3
SYSMUTE
level stored at data memory location LEVEL_VALUE to the
SSM2163 input addressed by the contents of location
INPUT_ADDR, and turns the Left and/or Right mixer channels
on/off based on bits 3 and 4 of INPUT_ADDR.
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. Interfacing the 80C51 µC to an SSM2163 in
3-Wire Mode
Port in 4-Wire Mode
In some cases, it may be desirable to synchronize the outputs of
several SSM2163s. The 4-wire mode, shown in Figure 30,
provides this capability. As shown in Figure 2, the Timing
Diagram, 4-Wire Mode, the input shift register is loaded with
data while the WRITE input is low. However, the data will not
be latched into the SSM2163’s internal registers until the
rising edge of the LOAD input. In this manner, any number
of SSM2163s can be loaded with data, while the amplitude and
mixer changes will not occur until the separate LOAD pulse
occurs.
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REV. 0