SSM2160_03 Datasheet, PDF (3/16 Pages) Analog Devices – 6-Channel, Serial Input Master/Balance Volume Controls

SSM2160
TIMING CHARACTERISTICS
Timing
Symbol
Description
Min
Typ
Max
Unit
t_CL
Input Clock Pulsewidth, Low
200
ns
t_CH
Input Clock Pulsewidth, High
200
ns
t_DS
Data Setup Time
50
ns
t_DH
Data Hold Time
75
ns
t_CW
Positive CLK Edge to End of Write
100
ns
t_WC
Write to Clock Setup Time
50
ns
t_LW
End of Load Pulse to Next Write
50
ns
t_WL
End of Write to Start of Load
50
ns
t_L
Load Pulsewidth
250
ns
t_W3
Load Pulsewidth (3-Wire Mode)
250
ns
NOTES
1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge.
2. For SPI™ or Microwire™ 3-wire bus operation, tie LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.)
3. If an idle HI clock is used, t_CW and t_WL are measured from the final negative transition to the idle state.
4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table.
5. Data must be sent MSB first.
0
CLK
1
1
DATA
0
1
WRITE
0
1
LD
0
D7
D6
D5
D4
D3
D2
D1
D0
1
CLK
0
1
DATA
0
1
WRITE
0
1
LD
0
t_CH
t_DS
D7
MSB
t_WC
t_CL
tDH
Figure 1. Timing Diagrams
t_CW
t_L
t_WL
t_LW
REV. A
–3–