ADC1130_15 Datasheet, PDF (3/4 Pages) Analog Devices – 14-Bit High Speed, Analog To-Digital Converters

Applyingthe ADC1130A, DC1131
IALOG INPUT CHARACTERISTICS
e input circuit of the ADCl130 and ADCll31
block diagram form.
are shown
:t5V
Range
+4.9994V
+2.5000V
+0.0006V
+O.OOOOV
-5.0000V
:tIOV
Range
+9.9988V
+5.0000V
+0.0012V
+O.OOOOV
-10.0000V
Offset Binary
Code
11111111111111
11000000000000
10000000000001
10000000000000
00000000000000
Two's Complement
Code
01111111111111
01000000000000
00000000000001
00000000000000
10000000000000
PIN 5
20V INPUT
Table I,. Nominal Bipolar Input-Output Relationships
PIN 6
10V INPUT
SERIAL DATA OUTPUT
PIN 19
BIPOLAR OFFSET
PIN 20
OFFSET ADJUST
PIN 23
GROUND SENSE
1.5M!]
5111
COMPARA TOR
The serial data output, available on Pin 32, is of the non-return-
to-zero format. The data is transmitted MSB first and is Binary
II ^{coded for unipolar units and Offset Binary coded for bipolar units.}
Figure 3, shown below, indicates one method for transmitting
Figure 2. Input Circuit Block Diagram
'hen the converters are connected as a unipolar device, Pin 19
left open circuit and, thus, no offset current is applied to the
om para tor input. The 0 to +lOV input signal applied to Pin 6
::Irthe 0 to +20V input signal applied to Pin 5) develops a 0 to
O_{4mA current which is compared to the 0 to -4mA output of}
B ^{he D/A converter. A voltage between +15V and -15 V can be}
pplied to Pin 20 from the wiper of a 100kD. potentiometer
S 0 adjust the zero point by ::t40LSB. To reduce the range of
his trim padding resistors should be used.
O _{Nith the offset output, Pin 22, connected to Pin 19, a +2mA}
L )ffset current is applied to the comparator inpu t. The
A.DC1l30 and ADCll31 will then accept bipolar inputs of
E _{t5V at Pin 6, or ::tlOV at Pin 5 and compare the 0 to +4mA}
T sum of the offset and input signal currents to the 0 to -4mA
\ ^{E D/A converter output. The offset adjustment potentiometer}
is once again used as described in the preceding paragraph.
data serially using only three wires (plus a digital ground). The
data is clocked into a receiving shift register using the delayed
clock output of the converter.
ADC1130/1131
32 SERIAL OUT
33 STATUS
35 CLOCKIN
36 CLOCKOUT
MSB
LSB STATUS
Figure 3. Serial Data Transmission
The timing diagram presented in Figure 4 shows that the con-
verter's clock output must be delayed by an amount of time
greater than or equal to the sum of the receiving shift register
setup time plus the 20ns clock output to serial output delay.
CLOCK
OUTPUT
I--- FIRST CLOCKPULSE --t--
r
J^.
SECONDCLOCKPULSE --j
I
Signal ground sense, Pin 23, should normally be jumpered to
I
malog ground, Pin 3. In the event that an offset voltage is
developed in the ground wiring, it may be possible to elimi-
nate its effect by connecting Pin 23 directly to the signal or
analog ground of the device feeding the analog input signal
SE RIAL
DATA
OUTPUT
I
I
!!/
.lJ_I. MS=B,
--1 i_I --- 20ns
\ BIT 2 = 0
to the ADc. In any case, Pin 23 must not be left open.
SHIFT
I
If a high input impedance is required, it can be achieved by
using a high speed operational amplifier as an input buffer.
~ REGISTER
STROBE
\
---1r-\
/
--.J ~
RECEIVING
SHIFT
PARALLEL DATA OUTPUT
II
REGISTER SETUP
TIME
These converters produce natural Binary Coded ou tpu ts when
configured as a unipolar device. As a bipolar device, they can
produce either Offset Binary or Two's Complement output
codes. The most significant bit is represented by Pin 72
(MSB output) for Binary and Offset Binary codes, or by Pin
70 (MSB output) for the Two's Complement code. Tables I
and II illustrate the relationship between analog input and
digital output for all three codes.
ANALOG INPUT
0 to +IOV
0 to +20V
Range
Range
+9.9994V
+J99988V
+5.0000V
+1.2500V
+0.0006V
+O.OOOOV
t 10.()000V
+2.5000V
+0.00 12V
+O.OOOOV
DIGITAL OUTPUT
Binary Code
11111111111111
10000000000000
00100000000000
00000000000001
00000000000000
Figure 4. Serial Data Timing Diagram
The 50ns span between the time that the last serial output bit
is available and the time that the STATUS output retUrns to
zero IIlsures that the data In the shift register will be valid on
the "I" to "0" transition of the STATUS signal.
GAIN AND OFFSET ADJUSTMENTS
The potentiometers used for making gain and offset adjust-
ments
arc connected as shown in l'igure 5. ~ote that
'15V
r-f ^ADJUST
1O0kll
GAIN _.15V
:==J ^{1 GAIN ADJUST}
, 15v
OFFSET
ADJUST
lOOk!>
15V
I
I
I
/L_-
19 BIPOLA" OFFSEl
20 OFFSET ADJUST
22 OFFSET OUTPUT
JUMPER CONNECTED
FOR BIPOLAR
OPERATION ONL Y
ADJUSTMENT RANGES
GAIN. t48LSB
OFFSET t40lSB
a jumper
Table I. Nominal Unioolar Inout-Outout Relationshios
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