ADC1130_15 Datasheet, PDF (1/4 Pages) Analog Devices – 14-Bit High Speed, Analog To-Digital Converters

r. ANALOG
W DEVICES
14-Bit HighSpeed,
Analogt-o-DigitalConverters
I
ADC1130/ADC1131
I
FEATURES
14-Bit Resolution and Accuracy
Fast 1211sConversion Time (ADC1131J/K)
Low 10ppmtC Maximum Gain TC
User Choice of Input Range
No Missing Codes
ADC1130fADC1131 FUNCTIONAL BLOCK DIAGRAM
GAIN ADJUST
3 I~
ANALOG
GROUND
5_~
2.5kil
6 1 olQ,V~~
- BIT2 ¹7⁷1²
170
67
.
APPLICA TIONS
PRECISION DAC
65
2.5kil
(-4mA FULL
OBSOLETE ^{Wide Band Data Digitizing}
Multichannel Computer Interface
High Accuracy Data Acquisition
X-Ray Tomography
Nuclear Accelerator Instrumentation
GENERAL DESCRIPTION
The ADC1l30 and ADCl131 are high speed analog-to-digital
converters packaged in a small 2" x 4" x 0.4" (51 x 102 x 10mm)
module, which perform complete 14-bit conversions in 2511s
and 1211srespectively. Using the successive approximations
technique, they convert analog input voltages into natural
binary, offset binary, or two's complement coded outputs.
Data outputs are provided in both parallel and non-return-to-
zero serial form.
SCALE OUTPun
5kil
19
20
22
23
27 I 0 +15V
SUCCESSIVE
APPROXIMA nON
LOGIC
29 0-- +5V
30 ¹ ~OIG.
GRD
32
SER. OUT
33
STATUS
34
CONVERT CMD
35
CLOCKIN
36
CLOCKOUT
63
61
58
56
54
52
50
48
.() 46
LSB1-31 44
43
SHORT
- CYCLE , 37
Four analog input ranges are available: 0 to +20V, 0 to +10V,
:!:10V, :!:5V. The user selects the desired range by making ap-
propriate connections to the module terminals. The ADC1130
and ADCl131 can also be connected so as to perform conver-
sions of less than 14 bit resolution with a proportionate de-
crease in conversion time.
CCOONMVMERATND-----I"""l
.. . . ^CLOCK
OUT
--IL11IUlJ1.
TIMING
As shown in Figure 1, the leading edge of the convert command
STATUS _--.J
L-
set the MSB output to Logic "0" and the CLOCK OUT,
STATUS, MSB, and BIT 2 through BIT 12 outputs to Logic
"1 ". Nothing further happens until the convert command re-
turns to Logic "0", at which time the clock starts to run and
the conversion proceeds.
With the MSB in the Logic "0" state, the internal digital-to-
analog converter's output is compared with the analog input.
If the DfA output is less than the analog input, the first "0" to
MSB
BIT 2 _---11
BIT3
BIT13
"1" clock transition resets the MSB to Logic" 1". If the Df A
output is greater than the analog input, the MSB remains at
Logic "0".
The first "0" to "1" clock transition also sets the BIT 2 output
to Logic "0" and another comparison is made. This process con-
tinues through each successive bit until the BIT 14 (LSB) com-
parison is completed. At this point the STATUS and CLOCK
OUT return to Logic "0" and the conversion cycle ends.
The serial data output is of the non-return-to-zero (NRZ) format.
The data is available, MSB first, 20ns after each of the four-
teen "0" to "1" clock transitions.
LSB _--1
U-
MSB
SERIAL
OUTPUT
----11
. . . . . . ^BIT2
BIT 13
.JLSB
MSB BIT 3
PREVIOUS WORD, 100. . 10
NEW WORD, 101. 01
Figure 1. Timing Diagram