AD9144 Datasheet, PDF (3/126 Pages) Analog Devices – Multiple chip synchronization

AD9144
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 6
Maximum DAC Update Rate Speed Specifications by Supply.....7
JESD204B Serial Interface Speed Specifications ...................... 7
SYSREF to DAC Clock Timing Specifications ......................... 8
Digital Input Data Timing Specifications ................................. 8
Latency Variation Specifications ................................................ 9
JESD204B Interface Electrical Specifications ........................... 9
AC Specifications........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Terminology .................................................................................... 15
Typical Performance Characteristics ........................................... 16
Theory of Operation ...................................................................... 21
Serial Port Operation ..................................................................... 22
Data Format ................................................................................ 22
Serial Port Pin Descriptions...................................................... 22
Serial Port Options ..................................................................... 22
Chip Information............................................................................ 24
Device Setup Guide ........................................................................ 25
Overview...................................................................................... 25
Step 1: Start Up the DAC ........................................................... 25
Step 2: Digital Datapath............................................................. 26
Step 3: Transport Layer .............................................................. 26
Step 4: Physical Layer................................................................. 27
Step 5: Data Link Layer.............................................................. 27
Step 6: Optional Error Monitoring .......................................... 28
Step 7: Optional Features........................................................... 28
DAC PLL Setup........................................................................... 29
Interpolation ............................................................................... 29
JESD204B Setup ......................................................................... 29
SERDES Clocks Setup................................................................ 31
Equalization Mode Setup .......................................................... 31
Link Latency Setup..................................................................... 31
Crossbar Setup ............................................................................ 33
JESD204B Serial Data Interface.................................................... 34
JESD204B Overview .................................................................. 34
Physical Layer ............................................................................. 35
Data Link Layer .......................................................................... 38
Transport Layer .......................................................................... 47
JESD204B Test Modes ............................................................... 60
JESD204B Error Monitoring..................................................... 61
Hardware Considerations ......................................................... 63
Digital Datapath ............................................................................. 67
Dual Paging ................................................................................. 67
Data Format ................................................................................ 67
Interpolation Filters ................................................................... 67
Digital Modulation..................................................................... 68
Inverse Sinc ................................................................................. 69
Digital Gain, Phase Adjust, DC Offset, and Group Delay.... 69
I to Q Swap .................................................................................. 70
NCO Alignment ......................................................................... 70
Downstream Protection ............................................................ 72
Datapath PRBS ........................................................................... 74
DC Test Mode ............................................................................. 74
Interrupt Request Operation ........................................................ 75
Interrupt Service Routine.......................................................... 75
DAC Input Clock Configurations ................................................ 76
Driving the CLK± Inputs .......................................................... 76
DAC PLL Fixed Register Writes ............................................... 76
Clock Multiplication .................................................................. 76
Starting the PLL.......................................................................... 78
Analog Outputs............................................................................... 79
Transmit DAC Operation.......................................................... 79
Device Power Dissipation.............................................................. 82
Temperature Sensor ................................................................... 82
Start-Up Sequence .......................................................................... 83
Step 1: Start Up the DAC........................................................... 83
Step 2: Digital Datapath............................................................. 83
Step 3: Transport Layer.............................................................. 84
Rev. A | Page 2 of 125