AD9144 Datasheet, PDF (106/126 Pages) Analog Devices – Multiple chip synchronization

Data Sheet
AD9144
Address Name
0x08C
DACLDOCNTRL1
0x08D
0x0E2
DACLDOCNTRL2
CAL_CTRL_GLOBAL
0x0E7
CAL_CLKDIV
0x0E8
CAL_PAGE
0x0E9
CAL_CTRL
Bit No.
[7:3]
[2:0]
Bit Name
RESERVED
REF_DIV_MODE
[7:0] DAC_LDO
[7:2] RESERVED
1
CAL_START_AVG
0
CAL_EN_AVG
[7:4] RESERVED
3
CAL_CLK_EN
[2:0] RESERVED
[7:4] RESERVED
[3:0] CAL_PAGE
7
CAL_FIN
6
CAL_ACTIVE
Settings
000
001
010
011
100
1
1
0
1
1
Description
Reserved.
Reference Clock Division Ratio. This field
controls the amount of division that is done
to the input clock at the CLK+/CLK− pins
before it is presented to the PLL as a reference
clock. The reference clock frequency must be
between 35 MHz and 80 MHz, but the
CLK+/CLK− input frequency can range from
35 MHz to 1 GHz. The user sets this division
to achieve a 35 MHz to 80 MHz PLL reference
frequency. For more details see the DAC PLL
Fixed Register Writes section.
1
2
4
8
16
DAC PLL LDO setting. This register must be
written to 0x7B for optimal performance.
Reserved.
Averaged Calibration Start. On rising edge,
calibrate the DACs. Only use if calibrating all
DACs.
Averaged Calibration Enable. Set prior to
starting calibration with CAL_START_AVG.
While this bit is set, calibration can be
performed, and the results are applied.
Enable averaged calibration
Must write the default value for proper
operation.
Enable Self Calibration Clock.
Enable calibration clock
Disable calibration clock
Reserved.
Reserved.
DAC Calibration Paging. Selects which of the
DACs are being accessed for calibration or
calibration readback. This paging affects
Register 0x0E9 and Register 0x0ED.
Calibration: any number of DACs can be
accessed simultaneously to write and
calibrate. Write a 1 to Bit x to include DAC x.
Readback: only one DAC at a time can be
accessed when reading back CAL_CTRL
(Register 0x0E9). Write a 1 to Bit x to read
from DAC x (the other bits must be 0).
Calibration finished. This bit is high when the
calibration has completed. If the calibration
completes and either CAL_ERRHI or CAL_
ERRLO is high, then the calibration cannot be
considered valid and are considered a timeout
event.
Calibration ran and is finished
Calibration Active. This bit is high while the
calibration is in progress.
Calibration is running
Reset
0x0
0x1
0x2B
0x0
0x0
0x0
0x3
0x0
0x0
0x0
0xF
0x0
0x0
Access
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R
R/W
R
R
Rev. A | Page 105 of 125