AD5689 Datasheet, PDF (3/24 Pages) Analog Devices – Dual, 16-/12-Bit nanoDAC+ with SPI Interface

Data Sheet
AD5689/AD5687
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE¹
AD5689
Resolution
Relative Accuracy
Differential Nonlinearity
AD5687
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
Offset Error Drift²
Gain Temperature Coefficient²
DC Power Supply Rejection Ratio²
DC Crosstalk²
OUTPUT CHARACTERISTICS²
Output Voltage Range
Capacitive Load Stability
Resistive Load³
Load Regulation
Short-Circuit Current⁴
Load Impedance at Rails⁵
Power-Up Time
REFERENCE INPUT
Reference Current⁶
Reference Input Range
Reference Input Impedance
LOGIC INPUTS²
Input Current
Input Low Voltage (VINL)
Input High Voltage (VINH)
Pin Capacitance
Min
Typ
Max
Unit
Test Conditions/Comments
16
±1
±2
±1
±3
±1
Bits
LSB
Gain = 2
Gain = 1
LSB
Guaranteed monotonic by design
12
Bits
±0.12 ±1
LSB
±1
LSB
Guaranteed monotonic by design
0.4
1.5
mV
All 0s loaded to DAC register
+0.1 ±1.5
mV
+0.01 ±0.1
% of FSR All 1s loaded to DAC register
±0.02 ±0.1
% of FSR
±0.01 ±0.1
% of FSR Gain = 2; TSSOP
±0.2
% of FSR Gain = 1; TSSOP
±1
µV/°C
±1
ppm
Of FSR/°C
0.15
mV/V
DAC code = midscale, VDD = 5 V ± 10%
±2
µV
Due to single-channel, full-scale output change
±3
µV/mA Due to load current change
±2
µV
Due to powering down (per channel)
0
VREF
V
Gain = 1
0
2 × VREF
V
Gain = 2; see Figure 23
2
nF
RL = ∞
10
nF
RL = 1 kΩ
1
kΩ
80
µV/mA 5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
80
µV/mA 3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
40
mA
25
Ω
See Figure 23
2.5
µs
Coming out of power-down mode; VDD = 5 V
90
µA
VREF = VDD = VLOGIC=5.5 V, gain = 1
180
µA
VREF = VDD = VLOGIC=5.5 V, gain = 2
1
VDD
V
Gain = 1
1
VDD/2
V
Gain = 2
16
kΩ
Gain = 1
32
kΩ
Gain = 2
0.7 × VLOGIC
2
±2
µA
0.3 × VLOGIC V
V
pF
Per pin
Rev. 0 | Page 3 of 24