ADSP-21992 Datasheet, PDF (29/48 Pages) Analog Devices – Mixed Signal DSP Controller With CAN

PRELIMINARY TECHNICAL DATA
August 2002
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ADSP-21992
External Port Read Cycle Timing
Table 10 and Figure 18 describe external port read operations. For additional information on the ACK signal, see the
discussion on on page 27.
Table 10. External Port Read Cycle Timing
Parameter Description^{1, 2, 3}
Min
Max
Unit
Switching Characteristics
t_CRA
EMI⁴ clock low to RD asserted delay
2.8
ns
t_CSRS
Chip select asserted to RD asserted delay
4.3
6.5
ns
t_ARS
Address valid to RD setup and delay
4.9
7.0
ns
t_AKS
ACK asserted to EMI clock high delay
6.0
ns
t_CRD
EMI clock low to RD de-asserted delay
2.5
2.7
ns
t_RSCS
RD de-asserted to chip select de-asserted setup
4.8
7.0
ns
t_RW
RD strobe pulsewidth
t_HCLK – 0.5
ns
t_RSA
RD de-asserted to address invalid setup
4.5
6.6
ns
Timing Requirements
t_AKW
ACK strobe pulsewidth
10.0
ns
t_CDA
RD to data enable access delay
0.0
ns
t_RDA
RD asserted to data access setup
t_HCLK – 5.5
ns
t_ADA
Address valid to data access setup
t_HCLK – 0.2
ns
t_SDA
Chip select asserted to data access setup
t_HCLK – 0.6
ns
t_SD
Data valid to RD de-asserted setup
1.8
ns
t_HRD
RD de-asserted to data invalid hold
0.0
ns
1_{tHCLK is the peripheral clock period.}
2_{These are preliminary timing parameters that are based on worst case operating conditions.}
3_{The pad loads for these timing parameters are 20 pF.}
4_{EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds}
to HCLK (at similar clock ratios).
REV. PrA ^{This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog}
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