ADSP-21992 Datasheet, PDF (16/48 Pages) Analog Devices – Mixed Signal DSP Controller With CAN

PRELIMINARY TECHNICAL DATA
ADSP-21992
For current information contact Analog Devices at [phone]
August 2002
1
GND
3
KEY (NO PIN)
5
BTMS
7
BTCK
9
BTRST
11
BTDI
13
GND
2
EMU
4
GND
6
TMS
8
TCK
10
TRST
12
TDI
14
TDO
TOP VIEW
Figure 7. JTAG Target Board Connector With No Local
Boundary Scan
The state of each standard JTAG signal can be found in
Table 4.
Table 4. State of Standard JTAG Signals¹
Signal Description
TMS
TCK
TRST
TDI
TDO
EMU
Test Mode Select
Test Clock (10 MHz)
Test Reset
Test Data In
Test Data Out
Emulation Pin
1_{O = Output, I = Input, o/d = Open Drain}
Emulator
O
O
O
O
I
I
DSP
I
I
I
I
O
O, o/d
The DSP CLKIN signal is the clock signal line (typically 30
MHz or greater) that connects an oscillator to all DSPs in
multiple DSP systems requiring synchronization. For syn-
chronous DSP operations to work correctly the CLKIN
signal on all the DSPs must be the same signal and the skew
between them must be minimal (use clock drivers, or other
means) – see the DSP users guide for more details on
CLKIN.
Note that the CLKIN signal is not used by the emulator and
can cause noise problems if connected to the JTAG header.
Legacy documents show it connected to pin 4 of the JTAG
header. Pin-4 should be tied to ground on the 14-pin JTAG
header (do not connect the JTAG header pin to the DSP
CLKIN signal). If you have already connected it to the
JTAG header pin, and are experiencing noise from this
signal, simply clip this pin on the 14-pin JTAG header.
The final connections between a single DSP target and the
emulation header (within 6 inches) are shown in Figure 8.
A 4.7K⍀ pull-up resistor has been added on TCK, TDI
and TMS chain for increased noise resistance.
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
JTAG
CONNECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
VDD
DSP
JTAG
PORT
EMU
EMU
GND
TMS
TCK
TRST
TMS
TCK
TRST
TDI
TDO
6 INCHES OR LESS
TDI
TDO
Figure 8. Single-DSP JTAG-Connections, Unbuffered
Should your design use more than one DSP (or other JTAG
device in the scan chain), or if your JTAG header is more
than 6 inches from the DSP, use a buffered connection
scheme as shown in Figure 9 (no local boundary scan mode
shown). To keep signal skew to a minimum, be sure the
buffers are all in the same physical package (typical chips
have 6, 8, or 16 drivers). Using a buffer that has built in
series resistors such as the 74ABT2244 family can help
reduce ringing on the JTAG signal lines. For low voltage
applications (3.3V, 2.5V, and 1.8V I/O), the 74ALVT, and
74AVC logic families are a good starting point. Also, note
the position of the pull-up resistor on EMU. This is
required since the EMU line is an open drain signal.
Important: If you have more than one DSP (or JTAG
device) on your target (in the scan chain), it is imperative
that you buffer the JTAG header. This will keep the signals
clean and avoid noise problems that occur with longer signal
traces (ultimately resulting in reliable emulator operation).
Although the theoretical number of devices that can be
supported (by the software) in one JTAG scan chain is quite
large (50 devices or more) it is not recommended that you
use more than eight physical devices in one scan chain. (A
physical device could however contain many JTAG devices
such as inside a multi-chip module). The recommendation
of not more than eight physical devices is mostly due to the
transmission line effects that appear in long signal traces,
and based on some field-collected empirical data. The best
approach for large numbers of physical devices is to break
the chain into several smaller independent chains, each with
their own JTAG header and buffer. If this is not possible,
at least add some jumpers that can reduce the number of
devices in one chain for debug purposes, and pay special
attention in the layout stage for transmission line effects.
16 ^{This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog}
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