AD9981_15 Datasheet, PDF (29/44 Pages) Analog Devices – High Performance 10-Bit Display Interface

AD9981
DETAILED 2-WIRE SERIAL CONTROL REGISTER DESCRIPTIONS
CHIP IDENTIFICATION
CLOCK GENERATOR CONTROL
0x00 7:0 Chip Revision
0x03 7:6 VCO Range Select
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
0x01 7:0 PLL Divide Ratio MSBs
The eight MSBs of the 12-bit PLL divide ratio PLLDIV.
The PLL derives a pixel clock from the incoming
Hsync signal. The pixel clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095 as long as the output frequency
is within range. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency.
VESA has established some standard timing specifi-
cations, which will assist in determining the value for
PLLDIV as a function of horizontal and vertical
display resolution and frame rate (see Table 9).
However, many computer systems do not conform
precisely to the recommendations and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV usually produces one or more vertical noise
bars on the display. The greater the error, the greater
the number of bars produced.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
Two bits that establish the operating range of the clock
generator. VCORNGE must be set to correspond to
the desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high
frequencies. For this reason, in order to output low
pixel rates and still get good jitter performance, the
PLL actually operates at a higher frequency but then
divides down the clock rate afterwards. See Table 13
for the pixel rates for each VCO range setting. The
PLL output divisor is automatically selected with the
VCO range setting. The power-up default value is 01.
Table 13. VCO Ranges
VCO Range
00
01
10
11
Pixel Rates
10 to 21
21 to 42
42 to 84
84 to 95
0x03 5:3 Charge Pump Current
Three bits that establish the current driving the loop
filter in the clock generator. The current must be set to
correspond with the desired operating frequency. The
power-up default value is current = 001.
Table 14. Charge Pump Currents
Ip2
Ip1
Ip0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Current
50
100
150
250
350
500
750
1500
0x03 2
External Clock Enable
0x02
The AD9981 updates the full divide ratio only when
the LSBs are written. Writing to this register by itself
does not trigger an update.
7:4 PLL Divide Ratio LSBs
The four LSBs of the 12-bit PLL divide ratio PLLDIV.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
This bit determines the source of the pixel clock.
Table 15. External Clock Select Settings
EXTCLK
Function
0
Internally generated clock
1
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external EXTCLK input pin. In
this mode, the PLL Divide Ratio (PLLDIV) is ignored.
The clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
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