AD9981_15 Datasheet, PDF (1/44 Pages) Analog Devices – High Performance 10-Bit Display Interface

FEATURES
10-bit analog-to-digital converter
95 MSPS maximum conversion rate
9% or less p-p PLL clock jitter at 95 MSPS
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsyncs counter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9981 is a complete, 10-bit, 95 MSPS, monolithic analog
interface optimized for capturing YPbPr video and RGB
graphics signals. Its 95 MSPS encode rate capability and full-
power analog bandwidth of 200 MHz supports all HDTV
video modes and graphics resolutions up to XGA (1024 × 768
at 85 Hz).
The AD9981 includes a 95 MHz triple ADC with an internal
reference, a PLL, programmable gain, offset, and clamp controls.
The user provides only 3.3 V and 1.8 V power supplies and an
analog input. Three-state CMOS outputs may be powered from
1.8 V to 3.3 V.
The AD9981’s on-chip PLL generates a sample clock from
the three-level sync (for YPbPr video) or the horizontal sync
(for RGB graphics). Sample clock output frequencies range from
10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at
95 MSPS.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
High Performance
10-Bit Display Interface
AD9981
FUNCTIONAL BLOCK DIAGRAM
PR/RED_IN1
PR/RED_IN0
2:1
MUX
CLAMP
10
AUTO OFFSET
PGA
10-BIT ¹⁰
ADC
10
AUTO OFFSET
AD9981
10
RED_OUT
Y/GREEN_IN1
Y/GREEN_IN0
2:1
MUX
CLAMP
PGA
10-BIT ¹⁰
ADC
10
AUTO OFFSET
10
GREEN_OUT
PB/BLUE_IN1
PB/BLUE_IN0
2:1
MUX
CLAMP
PGA
10-BIT ¹⁰
ADC
10
BLUE_OUT
HSYNC1
HSYNC2
VSYNC1
VSYNC2
SOGIN1
SOGIN2
EXTCLK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
DATACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFCM
REFLO
Figure 1.
With internal Coast generation, the PLL maintains its output
frequency in the absence of sync input. A 32-step sampling
clock phase adjustment is provided. Output data, sync, and
clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The AD9981 also
offers full sync processing for composite sync and sync-on-
green applications. A clamp signal is generated internally or
may be provided by the user through the CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9981 is
provided in a space-saving, 80-pin, Pb-free, LQFP surface
mount plastic package. It is specified over the 0°C to +70°C
temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.